Architecture support seems not risky, sure. Ideally it shouldn't be risky for any RISC-V CPU! What's less clear is everything else. Will this have RISC-V OS-A

Architecture support seems not risky, sure. Ideally it shouldn't be risky for any RISC-V CPU! What's less clear is everything else. Will this have RISC-V OS-A Platform Specification specification so it is ACPI compatible, or will this require custom baked devicetree for all its uncore? Will that uncore all be sifive provided uncore stuff or is microchip perhaps going to reuse some of their existing peripherals from other efforts? Which peripherals & busses will and won't have support in Linux, Zephyr, and the variety of other rtos? Will that support be upstreamed alike how excellently & persistently linux4sam was? As someone working for sifive I understand you want to present a good image, and I really hope the better cases do emerge here. I'm not worried about your RISC-V core working; it'll be great. I'm worried about how usable the rest of the chip will be & what level of support & upstreaming we'll see for that. Linux4sam is one of very very few arm players that has focused, for almost a decade now, on doing the right thing; most of the embedded ecosystem is fragmentary & not upstreamed & hard to use. Hence my comments & hopes. MicroSemi is definitely well known for some rad capable devices, good call there. But that was for a very different line-up, different offerings. Having a PIC that's targeting such elevated use cases is, to me, quite notable.