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Awesome to see. It'll be interesting to see what the level of support is. Does microchip float their own forked toolchain, or do Linux and Zephyr gain decent up

Awesome to see. It'll be interesting to see what the level of support is. Does microchip float their own forked toolchain, or do Linux and Zephyr gain decent upstream support for these systems? As commented already, linux4sam started an extremely strong forward footing for the old Ateml arm chips; if microchip can tap that same kind of smart can-do engineers to get support for pic64 good that would really be a massive turbocharger for this effoet. It's very very interesting & ultra-notable Microchip is shopping space-capable rad-hard editions, for mil use.

pkaye 2y ago
NASA JPL had selected Microchip and SiFive for making RISC-V SoC for future space missions so they probably planned to make similar chips for commercial customers. The one for JPL would be a RAD hardened versions.
brucehoult 2y ago
Why would you need a forked toolchain when you're using absolutely standards-compliant SiFive RISC-V cores? The same goes for Linux, Zephyr, FreeRTOS, NuttX and others ... all already work fine on RISC-V and have for years. Also, Microchip's MicroSemi division (acquisition in 2018) has long been supplying rad-tolerant and rad-hard FPGAs to the space industry, and MicroSemi has been supporting SiFive cores as a soft core in their FPGAs since 2017 and as a hard core (penta-core 64 bit @ 600-666 MHz) in the PolarFire SoC since 2021.
- jauntywundrkind 2y ago
  Architecture support seems not risky, sure. Ideally it shouldn't be risky for any RISC-V CPU! What's less clear is everything else. Will this have RISC-V OS-A Platform Specification specification so it is ACPI compatible, or will this require custom baked devicetree for all its uncore? Will that uncore all be sifive provided uncore stuff or is microchip perhaps going to reuse some of their existing peripherals from other efforts? Which peripherals & busses will and won't have support in Linux, Zephyr, and the variety of other rtos? Will that support be upstreamed alike how excellently & persistently linux4sam was? As someone working for sifive I understand you want to present a good image, and I really hope the better cases do emerge here. I'm not worried about your RISC-V core working; it'll be great. I'm worried about how usable the rest of the chip will be & what level of support & upstreaming we'll see for that. Linux4sam is one of very very few arm players that has focused, for almost a decade now, on doing the right thing; most of the embedded ecosystem is fragmentary & not upstreamed & hard to use. Hence my comments & hopes. MicroSemi is definitely well known for some rad capable devices, good call there. But that was for a very different line-up, different offerings. Having a PIC that's targeting such elevated use cases is, to me, quite notable.
  - brucehoult 2y ago
    I don't work for SiFive, and haven't for 4 1/2 years. I'm at a large company that is switching many of their consumer products from Arm to RISC-V.

pkaye 2y ago

NASA JPL had selected Microchip and SiFive for making RISC-V SoC for future space missions so they probably planned to make similar chips for commercial customers. The one for JPL would be a RAD hardened versions.

brucehoult 2y ago

Why would you need a forked toolchain when you're using absolutely standards-compliant SiFive RISC-V cores? The same goes for Linux, Zephyr, FreeRTOS, NuttX and others ... all already work fine on RISC-V and have for years. Also, Microchip's MicroSemi division (acquisition in 2018) has long been supplying rad-tolerant and rad-hard FPGAs to the space industry, and MicroSemi has been supporting SiFive cores as a soft core in their FPGAs since 2017 and as a hard core (penta-core 64 bit @ 600-666 MHz) in the PolarFire SoC since 2021.

jauntywundrkind 2y ago
Architecture support seems not risky, sure. Ideally it shouldn't be risky for any RISC-V CPU! What's less clear is everything else. Will this have RISC-V OS-A Platform Specification specification so it is ACPI compatible, or will this require custom baked devicetree for all its uncore? Will that uncore all be sifive provided uncore stuff or is microchip perhaps going to reuse some of their existing peripherals from other efforts? Which peripherals & busses will and won't have support in Linux, Zephyr, and the variety of other rtos? Will that support be upstreamed alike how excellently & persistently linux4sam was? As someone working for sifive I understand you want to present a good image, and I really hope the better cases do emerge here. I'm not worried about your RISC-V core working; it'll be great. I'm worried about how usable the rest of the chip will be & what level of support & upstreaming we'll see for that. Linux4sam is one of very very few arm players that has focused, for almost a decade now, on doing the right thing; most of the embedded ecosystem is fragmentary & not upstreamed & hard to use. Hence my comments & hopes. MicroSemi is definitely well known for some rad capable devices, good call there. But that was for a very different line-up, different offerings. Having a PIC that's targeting such elevated use cases is, to me, quite notable.
- brucehoult 2y ago
  I don't work for SiFive, and haven't for 4 1/2 years. I'm at a large company that is switching many of their consumer products from Arm to RISC-V.