3 ms·

> low cost PIC microcontrollers ahhh, I think there's the source of our confusion: I suspect you are actually talking about NOR flash? NOR flash is physically

> low cost PIC microcontrollers ahhh, I think there's the source of our confusion: I suspect you are actually talking about NOR flash? NOR flash is physically organized different from NAND. It typically does allow single word/byte or sometimes even bit level accesses, like you described. NOR flash is also much more reliable, often not needing any wear leveling at all. The downside is that NOR flash has orders of magnitudes lower data density. Microcontrollers would use NOR flash internally for program memory, precisely because it allows direct, single-cycle access to individual opcodes. With NAND flash, program memory would have to be read page-wise and require some sort of instruction cache in between. Other EEPROM-like devices (e.g. AT28Fxxx) also use NOR flash for pretty much the same reasons. On some embedded Linux devices, NOR flash is used for config/boot loader/kernel, while the rootfs lives on NAND.

SideQuark 2y ago
> ahhh, I think there's the source of our confusion: I suspect you are actually talking about NOR flash? Nope. PIC has on device NOR (which I've tested), and often has external NAND flash (depending on design choices), such as using SDCard interfaces. Here's [1] a Micron tech doc on their NAND chips stating quite clearly they allow exactly what I described doing above: "A NAND Flash block is 128KB. Erasing a block sets all bits to 1 (and all bytes to FFh). Programming is necessary to change erased bits from 1 to 0. The smallest entity that can be programmed is a byte." There's plenty of manufacturers and chip types that guarantee one can do this. It is tech notes like that led me to do some testing to see if devices fall into spec on R/W cycles before death when evaluating which chips to ship in consumer products that need this. [1] https://user.eng.umd.edu/~blj/CS-590.26/micron-tn2919.pdf https://user.eng.umd.edu/~blj/CS-590.26/micron-tn2919.pdf

SideQuark 2y ago

> ahhh, I think there's the source of our confusion: I suspect you are actually talking about NOR flash? Nope. PIC has on device NOR (which I've tested), and often has external NAND flash (depending on design choices), such as using SDCard interfaces. Here's [1] a Micron tech doc on their NAND chips stating quite clearly they allow exactly what I described doing above: "A NAND Flash block is 128KB. Erasing a block sets all bits to 1 (and all bytes to FFh). Programming is necessary to change erased bits from 1 to 0. The smallest entity that can be programmed is a byte." There's plenty of manufacturers and chip types that guarantee one can do this. It is tech notes like that led me to do some testing to see if devices fall into spec on R/W cycles before death when evaluating which chips to ship in consumer products that need this. [1] https://user.eng.umd.edu/~blj/CS-590.26/micron-tn2919.pdf https://user.eng.umd.edu/~blj/CS-590.26/micron-tn2919.pdf