> As we have seen, enabling SMT on a CPU core requires sharing many of the buffers and execution resources between the two logical processors. Even if there is

> As we have seen, enabling SMT on a CPU core requires sharing many of the buffers and execution resources between the two logical processors. Even if there is only one thread running on an SMT enabled core, these resources remain unavailable to that thread which reduces its potential performance. This isn't true (anymore?). We've seen a variety of SMT cores which partition the ROB, fetch/decode bandwidth, etc. when running in SMT mode but allow full use when not in SMT mode.