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> Speculative execution is so valuable for performance that a computer without it is completely unusable. If you really want a processor without it, buy an old

by toast0 2y ago

> Speculative execution is so valuable for performance that a computer without it is completely unusable. If you really want a processor without it, buy an old first-gen Pentium. Pentiums have branch prediction and speculative execution. You need to go back to i486 if you don't want speculative execution. Most of the socket 5/7 processors from other makers also had branch predictors and speculative execution, but not the Centaur Winchip. The Cyrix 5x86 for socket 3 (486) had speculative execution, but it was disabled by default and is reported to be buggy (but helps performance on published benchmarks).

pezezin 2y ago
According to Wikipedia, the original Pentium had branch prediction, but speculative execution was first implemented by the Pentium Pro: https://en.wikipedia.org/wiki/P6_(microarchitecture)#Features https://en.wikipedia.org/wiki/P6_(microarchitecture)#Feature...
- gpderetta 2y ago
  The wiki is wrong or at least misleading. Branch prediction is a form of speculative execution. Even 486 (and possibly 386) had branch prediction (although a trivial one). P6 was a huge deal because it added out of order execution. Edit: I guess it is a matter of semantics: in the classical 5 stage in order RISC, instructions after the speculated branch are fetched, decoded, etc, but they won't reach the execution stage before the speculation is resolved, so only the branch is technically "executed" speculatively at the fetch stage. So there is less state to unwind, compared to a true OoO machine that can run ahead.
  - to11mtm 2y ago
    according to this thing I found [0] the 486 has a predictor for the branch not taken. Not sure what that means but it looks like it's mostly for the instruction fetch/decode based on other notes. Ironically sounds close to your 5 stage RISC description, extra ironic because 486 is 5 stages too... P5 has a more 'real' BP but also had the U/V Pipelining. But yes as far as OoO goes, I think for x86 it was Nx586 first, then PPro (P6), then Cyrix 6x86 [1] and AMD K6 (courtesy of Nextgen tech) the next year. [0] - https://people.computing.clemson.edu/~mark/330/colwell/case_486.html https://people.computing.clemson.edu/~mark/330/colwell/case_... [1] - Worth noting the Cyrix Coma bug, which was a way to express a flaw in the pipeline. https://en.wikipedia.org/wiki/Cyrix_coma_bug https://en.wikipedia.org/wiki/Cyrix_coma_bug
    - gpderetta 2y ago
      As far as I know 486 predicted all branches as not taken, so it would fetch and decide instructions after a branche and throw that away when the speculation was proven wrong. I guess calling this speculative execution is a stretch.

by toast0 2y ago

pezezin 2y ago

According to Wikipedia, the original Pentium had branch prediction, but speculative execution was first implemented by the Pentium Pro: https://en.wikipedia.org/wiki/P6_(microarchitecture)#Features https://en.wikipedia.org/wiki/P6_(microarchitecture)#Feature...

gpderetta 2y ago
The wiki is wrong or at least misleading. Branch prediction is a form of speculative execution. Even 486 (and possibly 386) had branch prediction (although a trivial one). P6 was a huge deal because it added out of order execution. Edit: I guess it is a matter of semantics: in the classical 5 stage in order RISC, instructions after the speculated branch are fetched, decoded, etc, but they won't reach the execution stage before the speculation is resolved, so only the branch is technically "executed" speculatively at the fetch stage. So there is less state to unwind, compared to a true OoO machine that can run ahead.
- to11mtm 2y ago
  according to this thing I found [0] the 486 has a predictor for the branch not taken. Not sure what that means but it looks like it's mostly for the instruction fetch/decode based on other notes. Ironically sounds close to your 5 stage RISC description, extra ironic because 486 is 5 stages too... P5 has a more 'real' BP but also had the U/V Pipelining. But yes as far as OoO goes, I think for x86 it was Nx586 first, then PPro (P6), then Cyrix 6x86 [1] and AMD K6 (courtesy of Nextgen tech) the next year. [0] - https://people.computing.clemson.edu/~mark/330/colwell/case_486.html https://people.computing.clemson.edu/~mark/330/colwell/case_... [1] - Worth noting the Cyrix Coma bug, which was a way to express a flaw in the pipeline. https://en.wikipedia.org/wiki/Cyrix_coma_bug https://en.wikipedia.org/wiki/Cyrix_coma_bug
  - gpderetta 2y ago
    As far as I know 486 predicted all branches as not taken, so it would fetch and decide instructions after a branche and throw that away when the speculation was proven wrong. I guess calling this speculative execution is a stretch.