I've built VLIW hardware, virtualisation is not an issue, cache usage is not different than other CPUs - in fact modern superscalar, out-of-order CPUs effective

I've built VLIW hardware, virtualisation is not an issue, cache usage is not different than other CPUs - in fact modern superscalar, out-of-order CPUs effectively do what the compiler for VLIWs do dynamically on the fly. The big issue about VLIW hardware is that it tends to address a particular performance point - usually lets you squeeze out the last bit of performance without having to go to the complexity of dynamic instruction scheduling (and doubling the CPU size) - the problem comes when you want to do your next chip and the trade off ends up being different, you can't keep the same instruction set and so making an ARCHITECTURE is hard