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> Instead of one path forward there are now many. This is a feature, not a bug. Leading edge nodes are becoming harder and harder to develop on, particularly

by KK7NIL 2y ago

> Instead of one path forward there are now many. This is a feature, not a bug. Leading edge nodes are becoming harder and harder to develop on, particularly outside of memory and logic. This is because of limitations in terms of Ft, max voltage, layout, poor scaling of analog, etc. Leading edge nodes nowadays generally release without a lot of key features and so can only be used for compute tiles, requiring other tiles for IO, analog circuits, etc. As the nodes mature these features will generally get added on (that might not even be possible in the future if the current trend continues), at which point you can do a SoC with all these things integrated on one die (which was essentially the only option before we had the packaging technology for heterogeneous chiplet systems). This is why heterogeneous chiplet designs are the future. Source: my job is helping to develop and test analog and mixed signal circuits on leading edge nodes at Intel.

kurthr 2y ago
Totally agree, the complexity of 3D, heterogeneous nodes, and chiplet integration are necessary. Thank you for your efforts, and I wish you great success. It's just that for over 50 years optimizing transistor pitch in 2D was sufficient to drive demand and investment. The clear winning single path forward provided the exponential growth we've come to expect. I suspect the complexity and uncertainty of this new heterogeneity does not. Underlying system and process simplicity and reliability support overlaying complexity in software and network. I started in semi with 68020/30 to see the huge jump from 2um to 0.8um and stayed in on the trailing edge of analog down to 28nm. Maybe there is another 40 years of growth, but it feels like even though 3D stacking increases the power law of dimensionality, it may reduce iteration rate more. We've got 8 high HBM, but will we have 100 in even 8 years or 1000 in another 8 more?
- KK7NIL 2y ago
  > We've got 8 high HBM, but will we have 100 in even 8 years or 1000 in another 8 more? No, probably not, but that's not the point. The point is that now memory and logic (in case of HBM) can be further decoupled, allowing us to use processes optimized for each, instead of having to compromise one for the other. This will allow for cheaper and faster iteration. You're correct that 3D scaling will likely not go very far, but that's not the key part; the ability to tightly couple heterogeneous dies, allowing for specialization and decoupling of processes, is the key to further scaling.

by KK7NIL 2y ago

kurthr 2y ago

Totally agree, the complexity of 3D, heterogeneous nodes, and chiplet integration are necessary. Thank you for your efforts, and I wish you great success. It's just that for over 50 years optimizing transistor pitch in 2D was sufficient to drive demand and investment. The clear winning single path forward provided the exponential growth we've come to expect. I suspect the complexity and uncertainty of this new heterogeneity does not. Underlying system and process simplicity and reliability support overlaying complexity in software and network. I started in semi with 68020/30 to see the huge jump from 2um to 0.8um and stayed in on the trailing edge of analog down to 28nm. Maybe there is another 40 years of growth, but it feels like even though 3D stacking increases the power law of dimensionality, it may reduce iteration rate more. We've got 8 high HBM, but will we have 100 in even 8 years or 1000 in another 8 more?

KK7NIL 2y ago
> We've got 8 high HBM, but will we have 100 in even 8 years or 1000 in another 8 more? No, probably not, but that's not the point. The point is that now memory and logic (in case of HBM) can be further decoupled, allowing us to use processes optimized for each, instead of having to compromise one for the other. This will allow for cheaper and faster iteration. You're correct that 3D scaling will likely not go very far, but that's not the key part; the ability to tightly couple heterogeneous dies, allowing for specialization and decoupling of processes, is the key to further scaling.