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No. Actually, the state of the art of EDA software is worse. My project has been to design (and create) better EDA software that will simulate, optimize and th

No. Actually, the state of the art of EDA software is worse. My project has been to design (and create) better EDA software that will simulate, optimize and therefore can form and place each individual transistor optimally to achieve lower power, higher speed and lower cost. There is only one drawback over all existing EDA software: my EDA tools must run on a ($100k) small supercomputer or FPGA cluster because it deals with a billionfold more transistors than existing EDA software and that takes more compute. It means my software is much cheaper than existing EDA software but will yield much better chips and wafers with much faster, better, cheaper and fewer transistors. A high level overview of my software is mentioned indirectly in my talk https://vimeo.com/731037615 https://vimeo.com/731037615 I'm eager to give a talk on my EDA software as well, please consider inviting me to give it? Other researchers and companies have proven that optimizing transistor design and placement over standard cell libraries and PDKs can be done, for example: https://www.micromagic.com/news/Ultra-Low-Power_PressRelease.pdf https://www.micromagic.com/news/Ultra-Low-Power_PressRelease... was done with their own EDA software. I am very certain (but have no hard proof) that this is what Apple did on their M1, M2, M3. M4 and M5 processors, especially their high end M2 and M5 Ultra chips. What I'm claiming here is that humanity can design three to four orders of magnitude faster computer chips using at least two orders of magnitudes less energy making chips orders of magnitude cheaper if we only used better EDA software (CAD=> SYM=> FAB) that we use today. Moore's law is not at an end. I'd be happy to provide proof of this, but that takes a bit more effort than a HN comment.

hansihe 2y ago
I don't know about this at any detailed level, but doesn't designing standard cells for leading edge nodes involve a lot of trial and error? Is a lot of the issues that can occur even well understood to the level that it can be simulated? With the approach you mention, would it involve creating "custom standard cells", or would the software allow placement of every transistor outside of even a standard cell grid? If the latter, I would have trouble believing it could be feasible with the order of magnitude of computing power we have available to us today.
- morphle 2y ago
  The best results will be with custom shapes and custom individual placement of every transistor outside standard cell but within the PDK rules. Going outside the PDK rules will be even better but also harder. The trial and error you do mostly by simulating your transistors which you than validate by making the wafers. You can simulate with mathematical models (for example in SPICE) but you should eventually try to simulate at the molecular, the atom/electron/photon and even at the quantum level, but each finer grained simulation level will take orders of magnitude more compute resources. Chip quality is indeed limited by the magnitude of computing power and software: to design better (super)computer chips you need supercomputers. We designed a WSI (wafer scale integration) with a million core processors and terabytes of SRAM on a wafer with 45 trillion transistors that we won't chip into chips. It would cost roughly $20K in mass production and would be the fastest cheapest desktop supercomputer to run my EDA software on so you could design even better transistors for the next step. We also designed a $800 WSI 180nm version with 16000 cores with the same transitors as the Pentium chip in the RightTo article.
  - isotypic 2y ago
    Has this WSI chip been taped out/verified? I must admit I am somewhat skeptical of TBs of SRAM, even at wafer scale integration. What would the power efficiency/cooling look like?
    - morphle 2y ago
      The full WSI with 10 billion transistors at 180nm has not been taped out yet, I need $100K investment for that. This has 16K processors and a few megabyte SRAM. I taped out 9 mm2 test chips to test transistors, the processors, programmable Morphle Logic and interconnects. The ultra-low power 3nm WSI with trillions of transistors anda Terabyte SRAM will draw a megaWatt and would melt the transistors. So we need to simulate the transitors better and lower to power to 2 to 3 terawatt. There is a youtube video of a teardown of the Cerebras WSI cooling system where they mention the cooling and power numbers. They also mention that they also modeled their WSI on their own supercomputer, their previous WSI.
avnd 2y ago
That’s a very ambitious project to say the least and I’ll bite! Please elaborate Also, have you checked out the OpenROAD[1] project? It’s a pretty impressive open source RTL to GDSII flow. I went to their most recent meetup at DAC’24 and there’s a great community around the project. [1] https://theopenroadproject.org/ https://theopenroadproject.org/
- morphle 2y ago
  >Please elaborate I'd love to but what do you want me to elaborate on? We started making EDA tools and simulators (CAD, SYM FAB as Alan Kay says) and designing a wafer scale integration to run parallel Squeak Smalltalk (David Ungar's ROARVM) in 2007 and we are still working on it in 2024 so I estimate 30,000 hours now. I call that very ambitious too. >Also, have you checked out the OpenROAD[1] project? It’s a pretty impressive No it is not pretty impressive EDA software, OpenROAD software quality is like Linux, " a budget of bad ideas" as Alan Kay typifies it. Openroad is decades old sequential program code, millions of lines of ancient C, C++ and bits of Python programs written in the very low level C language, riddled with bugs and pathes. The tools are bolted together with primitive scripts and very finicky configurations and parametric rules. Not that the commercial proprietary EDA software is any better, that usually is even worse but because you don't see the source code you can't see the underlying mess. Good EDA tools should be written by just a few expert programmers and scientists in just a few thousand lines of code and run on a supercomputer. So the first ambitous goal is to learn how to write better software (than the current dozens of millions of lines of EDA software code). Alan Kay explains how [1-3]: [1] https://www.youtube.com/watch?v=ubaX1Smg6pY https://www.youtube.com/watch?v=ubaX1Smg6pY [2] https://www.youtube.com/watch?v=Kj4fLRm2UC4 https://www.youtube.com/watch?v=Kj4fLRm2UC4 [3] https://www.youtube.com/watch?v=1e8VZlPBx_0 https://www.youtube.com/watch?v=1e8VZlPBx_0 The second ambitous goal is to (learn to) design ultra low power transistor and free space optics. Learn from the best quantum physicists: [4]. https://www.youtube.com/watch?v=-dQoImLNgWs https://www.youtube.com/watch?v=-dQoImLNgWs The biggest problem is you need to get a couple of million investment just to test your software with a few tape-outs. I only managed to invest the money for the 30,000 hours of labour so far, you can guess how many millions that's worth.
  - 2y ago
BobbyTables2 2y ago
Could this be parallelized with a GPU?
- morphle 2y ago
  I wouldn't want to do that, GPU compilers are not open source and the hardware is undocumented. As a scientist I feel they are extremely badly designed. My transistor and atomic simulation software is extremely parallel but not in the limited SIMD way that GPU's are.
initramfs 2y ago
Hello, I am interested in your research as well as MicroMagics. The Claremont (32nm Pentium) and MicroMagic are the only application processors that have utilized NTV by stabilizing the voltage at 350mV-500mV. I started a project to make solar powerable mobile devices https://hackaday.io/project/177716-the-open-source-autarkic-motherboard https://hackaday.io/project/177716-the-open-source-autarkic-... My email is available in the github's linked. There are other processors, such as Ambiq Micro, but they are Cortex M4 and M55: https://www.top-electronics.com/en/apollo510-soc-250mhz-3-75mb-wlcsp https://www.top-electronics.com/en/apollo510-soc-250mhz-3-75...
- morphle 2y ago
  We've designed $0,10 ultra low power 8/16/32/64 bit processor SoC with built in MPPT buck/boost converters so they can be powered directly from single solar cells or small charge Li-ion cells. They have low power networking so you can create clusters. I'm not sure yet if they will be even lower power than you 5 mW processors but 1 mW is our aim. I would argue that a solar powered computer would benefit from a 2 megabyte (could be as low as 128KB) SRAM operating system with GUI like Squeak or Smalltalk-80 instead of a Linux as you propose. We've learned a lot from the low power OLPC designs. Thanks for the invite, I'm eager to collaborate on your solar powered computers but I'm having trouble finding your email in your githubs. Could you email us morphle73 at g mail dot com?
  - initramfs 2y ago
    Thanks, it is giovanni dot los___ at gmail.com (it should be in your inbox) Also, Ambiq Micro has a 2MB MRAM (+2.75MB SRAM) processor https://www.top-electronics.com/en/apollo4-blue-plus-192-mhz-2-75mb-bga https://www.top-electronics.com/en/apollo4-blue-plus-192-mhz... that can run on solar power (it uses ~5uA/MHz, Cortex M4) and Andreas Eriksen got LISP text editor to run on 384K RAM with the Apollo3 https://hackaday.io/project/184340-potatop https://hackaday.io/project/184340-potatop and 4'4" Memory In Pixel Display. I read that lithium-ion capacitors have much faster charging than regular li-on. https://www.tindie.com/products/jaspersikken/solar-harvesting-into-lithium-ion-capacitor/ https://www.tindie.com/products/jaspersikken/solar-harvestin... (and longer lifespan)
initramfs 2y ago
I read this is the software they used to make the MicroMagic https://sourceforge.net/projects/mmi-pd https://sourceforge.net/projects/mmi-pd (someone on The Open-Source Silicon Slack mentioned it, I think https://open-source-silicon.dev/ https://open-source-silicon.dev/
anamax 2y ago
A few decades ago, Quickturn sold a custom-built FPGA cluster to do hardware simulation at the gate level. Quickturn was bought by Cadence and now seems to be gone.
- FastFT 2y ago
  Not sure if its from Quickturn’s acquisition, but Cadence still makes a hardware simulation platform called Palladium.
therealcamino 2y ago
If you have working software that gives orders of magnitude improvements, needing $100k worth of hardware would be no barrier at all. That's a fraction of just the EDA software license budget for many projects.

hansihe 2y ago

I don't know about this at any detailed level, but doesn't designing standard cells for leading edge nodes involve a lot of trial and error? Is a lot of the issues that can occur even well understood to the level that it can be simulated? With the approach you mention, would it involve creating "custom standard cells", or would the software allow placement of every transistor outside of even a standard cell grid? If the latter, I would have trouble believing it could be feasible with the order of magnitude of computing power we have available to us today.

morphle 2y ago
The best results will be with custom shapes and custom individual placement of every transistor outside standard cell but within the PDK rules. Going outside the PDK rules will be even better but also harder. The trial and error you do mostly by simulating your transistors which you than validate by making the wafers. You can simulate with mathematical models (for example in SPICE) but you should eventually try to simulate at the molecular, the atom/electron/photon and even at the quantum level, but each finer grained simulation level will take orders of magnitude more compute resources. Chip quality is indeed limited by the magnitude of computing power and software: to design better (super)computer chips you need supercomputers. We designed a WSI (wafer scale integration) with a million core processors and terabytes of SRAM on a wafer with 45 trillion transistors that we won't chip into chips. It would cost roughly $20K in mass production and would be the fastest cheapest desktop supercomputer to run my EDA software on so you could design even better transistors for the next step. We also designed a $800 WSI 180nm version with 16000 cores with the same transitors as the Pentium chip in the RightTo article.
- isotypic 2y ago
  Has this WSI chip been taped out/verified? I must admit I am somewhat skeptical of TBs of SRAM, even at wafer scale integration. What would the power efficiency/cooling look like?
  - morphle 2y ago
    The full WSI with 10 billion transistors at 180nm has not been taped out yet, I need $100K investment for that. This has 16K processors and a few megabyte SRAM. I taped out 9 mm2 test chips to test transistors, the processors, programmable Morphle Logic and interconnects. The ultra-low power 3nm WSI with trillions of transistors anda Terabyte SRAM will draw a megaWatt and would melt the transistors. So we need to simulate the transitors better and lower to power to 2 to 3 terawatt. There is a youtube video of a teardown of the Cerebras WSI cooling system where they mention the cooling and power numbers. They also mention that they also modeled their WSI on their own supercomputer, their previous WSI.

avnd 2y ago

That’s a very ambitious project to say the least and I’ll bite! Please elaborate Also, have you checked out the OpenROAD[1] project? It’s a pretty impressive open source RTL to GDSII flow. I went to their most recent meetup at DAC’24 and there’s a great community around the project. [1] https://theopenroadproject.org/ https://theopenroadproject.org/

morphle 2y ago
>Please elaborate I'd love to but what do you want me to elaborate on? We started making EDA tools and simulators (CAD, SYM FAB as Alan Kay says) and designing a wafer scale integration to run parallel Squeak Smalltalk (David Ungar's ROARVM) in 2007 and we are still working on it in 2024 so I estimate 30,000 hours now. I call that very ambitious too. >Also, have you checked out the OpenROAD[1] project? It’s a pretty impressive No it is not pretty impressive EDA software, OpenROAD software quality is like Linux, " a budget of bad ideas" as Alan Kay typifies it. Openroad is decades old sequential program code, millions of lines of ancient C, C++ and bits of Python programs written in the very low level C language, riddled with bugs and pathes. The tools are bolted together with primitive scripts and very finicky configurations and parametric rules. Not that the commercial proprietary EDA software is any better, that usually is even worse but because you don't see the source code you can't see the underlying mess. Good EDA tools should be written by just a few expert programmers and scientists in just a few thousand lines of code and run on a supercomputer. So the first ambitous goal is to learn how to write better software (than the current dozens of millions of lines of EDA software code). Alan Kay explains how [1-3]: [1] https://www.youtube.com/watch?v=ubaX1Smg6pY https://www.youtube.com/watch?v=ubaX1Smg6pY [2] https://www.youtube.com/watch?v=Kj4fLRm2UC4 https://www.youtube.com/watch?v=Kj4fLRm2UC4 [3] https://www.youtube.com/watch?v=1e8VZlPBx_0 https://www.youtube.com/watch?v=1e8VZlPBx_0 The second ambitous goal is to (learn to) design ultra low power transistor and free space optics. Learn from the best quantum physicists: [4]. https://www.youtube.com/watch?v=-dQoImLNgWs https://www.youtube.com/watch?v=-dQoImLNgWs The biggest problem is you need to get a couple of million investment just to test your software with a few tape-outs. I only managed to invest the money for the 30,000 hours of labour so far, you can guess how many millions that's worth.
- 2y ago

BobbyTables2 2y ago

Could this be parallelized with a GPU?

morphle 2y ago
I wouldn't want to do that, GPU compilers are not open source and the hardware is undocumented. As a scientist I feel they are extremely badly designed. My transistor and atomic simulation software is extremely parallel but not in the limited SIMD way that GPU's are.

initramfs 2y ago

Hello, I am interested in your research as well as MicroMagics. The Claremont (32nm Pentium) and MicroMagic are the only application processors that have utilized NTV by stabilizing the voltage at 350mV-500mV. I started a project to make solar powerable mobile devices https://hackaday.io/project/177716-the-open-source-autarkic-motherboard https://hackaday.io/project/177716-the-open-source-autarkic-... My email is available in the github's linked. There are other processors, such as Ambiq Micro, but they are Cortex M4 and M55: https://www.top-electronics.com/en/apollo510-soc-250mhz-3-75mb-wlcsp https://www.top-electronics.com/en/apollo510-soc-250mhz-3-75...

morphle 2y ago
We've designed $0,10 ultra low power 8/16/32/64 bit processor SoC with built in MPPT buck/boost converters so they can be powered directly from single solar cells or small charge Li-ion cells. They have low power networking so you can create clusters. I'm not sure yet if they will be even lower power than you 5 mW processors but 1 mW is our aim. I would argue that a solar powered computer would benefit from a 2 megabyte (could be as low as 128KB) SRAM operating system with GUI like Squeak or Smalltalk-80 instead of a Linux as you propose. We've learned a lot from the low power OLPC designs. Thanks for the invite, I'm eager to collaborate on your solar powered computers but I'm having trouble finding your email in your githubs. Could you email us morphle73 at g mail dot com?
- initramfs 2y ago
  Thanks, it is giovanni dot los___ at gmail.com (it should be in your inbox) Also, Ambiq Micro has a 2MB MRAM (+2.75MB SRAM) processor https://www.top-electronics.com/en/apollo4-blue-plus-192-mhz-2-75mb-bga https://www.top-electronics.com/en/apollo4-blue-plus-192-mhz... that can run on solar power (it uses ~5uA/MHz, Cortex M4) and Andreas Eriksen got LISP text editor to run on 384K RAM with the Apollo3 https://hackaday.io/project/184340-potatop https://hackaday.io/project/184340-potatop and 4'4" Memory In Pixel Display. I read that lithium-ion capacitors have much faster charging than regular li-on. https://www.tindie.com/products/jaspersikken/solar-harvesting-into-lithium-ion-capacitor/ https://www.tindie.com/products/jaspersikken/solar-harvestin... (and longer lifespan)

initramfs 2y ago

I read this is the software they used to make the MicroMagic https://sourceforge.net/projects/mmi-pd https://sourceforge.net/projects/mmi-pd (someone on The Open-Source Silicon Slack mentioned it, I think https://open-source-silicon.dev/ https://open-source-silicon.dev/

anamax 2y ago

A few decades ago, Quickturn sold a custom-built FPGA cluster to do hardware simulation at the gate level. Quickturn was bought by Cadence and now seems to be gone.

FastFT 2y ago
Not sure if its from Quickturn’s acquisition, but Cadence still makes a hardware simulation platform called Palladium.

therealcamino 2y ago

If you have working software that gives orders of magnitude improvements, needing $100k worth of hardware would be no barrier at all. That's a fraction of just the EDA software license budget for many projects.