4 ms·
This is cool, but note: * ~~It requires two passes over the data to hash (notice the two while loops).~~ Actually it doesn't. * The first loop casts the data
by ronsor 2y ago
This is cool, but note:
* ~~It requires two passes over the data to hash (notice the two while loops).~~ Actually it doesn't.
* The first loop casts the data pointer to a 64-bit int, so you will get different results depending on endianness. I don't remember if this is undefined behavior or not.
- benhoyt 2y agoI could be wrong, but I think it just goes over the data once. The first loop increments i by 8, so is processing 64 bits at a time. It looks like the second loop only does the remaining few bytes, if any.
- deleted 2y ago[deleted]
- bobmcnamara 2y agoIt's not the endianness that's undefined, it's the dereferencing. 75% chance of this causing an alignment trap on my current development target.
- jsheard 2y agoAnd even on platforms that allow unaligned access, isn't there usually a performance penalty when the access straddles two cache lines? Still best avoided if possible.
- bobmcnamara 2y agoI don't often deal with CPU-coupled caches, but I could see a system where that happens. Cortex-M4, which doesn't have integrated caches, breaks each 32-bit load into 1-3 aligned loads of between 8 and 32 bits according to the address %4. Cortex-M7 performs each 32-bit load as either 1x or 2x 32-bit aligned loads depending on address % 4. I agree - especially in cases like this algorithm, where there is only one memory stream, it's often worth unrolling up to 3 or 7 accesses before the big aligned loop.