4 ms·
https://en.wikipedia.org/wiki/Apple_M1#CPU https://en.wikipedia.org/wiki/Apple_M1#CPU: “The high-performance cores have an unusually large 192 KB of L1 instruc
by Someone 2y ago
https://en.wikipedia.org/wiki/Apple_M1#CPU https://en.wikipedia.org/wiki/Apple_M1#CPU:
“The high-performance cores have an unusually large 192 KB of L1 instruction cache and 128 KB of L1 data cache and share a 12 MB L2 cache; the energy-efficient cores have a 128 KB L1 instruction cache, 64 KB L1 data cache, and a shared 4 MB L2 cache.”
⇒ chances are you don’t even have to try to fit an emulator of a 8-bit machine and it memory into the L1 cache.
- filleduchaos 2y agoI think you would very much have to try to fit a complete emulator of, say, the Game Boy into 128 + 64KB. There's plenty of behaviour that is self-evident on real silicon but verbose and tricky to express in software.
- throwaway2037 2y agoReal question about L1 caches. For a long time, x86 (Intel & AMD) L1 caches have been pretty much pegged at 32KB. Do you know why they didn't make them larger? My guess: There is a trade-off between economics and performance.
- account42 2y agoThere is a trade-off between cache size and latency.
- throwaway2037 2y agoOk, so why do the new Mx chips from Apple have an L1 cache size greater than 32KB? Did they solve some long standing design issue?