Intel's explanation (at section 15.12): https://cdrdv2.intel.com/v1/dl/getContent/814198?fileName=248966-Optimization-Reference-Manual-V1-050.pdf#G16.92586 http

Intel's explanation (at section 15.12): https://cdrdv2.intel.com/v1/dl/getContent/814198?fileName=248966-Optimization-Reference-Manual-V1-050.pdf#G16.92586 https://cdrdv2.intel.com/v1/dl/getContent/814198?fileName=24... > In Intel microarchitectures prior to Skylake, the SSE divide and square root instructions DIVPS and SQRTPS have a latency of 14 cycles (or the neighborhood) and they are not pipelined. This means that the throughput of these instructions is one in every fourteen cycles. The 256-bit Intel AVX instructions VDIVPS and VSQRTPS execute with 128-bit data path and have a latency of twenty-eight cycles and they are not pipelined as well. > In microarchitectures that provide DIVPS/SQRTPS with high latency and low throughput, it is possible to speed up single-precision divide and square root calculations using the (V)RSQRTPS and (V)RCPPS instructions. For example, with 128-bit RCPPS/RSQRTPS at five-cycle latency and one-cycle throughput or with 256-bit implementation of these instructions at seven-cycle latency and two-cycle throughput, a single Newton-Raphson iteration or Taylor approximation can achieve almost the same precision as the (V)DIVPS and (V)SQRTPS instructions (emphasis mine)