To your point about i/o bottlenecks....these days, there is an i/o bottleneck between main memory and the registers--and even between the registers and the ALUs

To your point about i/o bottlenecks....these days, there is an i/o bottleneck between main memory and the registers--and even between the registers and the ALUs. This changes the tradeoffs. And its why we use chips sporting data parallelism and pipelined floating point units. Both techniques are, in the final analysis, backing off of pure RISC and making more complex instructions.