> "tailoring the hardware for specific languages" "hardware" in quotes. A bunch of the machines had no/little language specific hardware. For example an Xerox

> "tailoring the hardware for specific languages" "hardware" in quotes. A bunch of the machines had no/little language specific hardware. For example an Xerox Interlisp-D machine was the same hardware like the Smalltalk or Mesa system. The microcode was different. The microcode provided the instruction set and then the machine would boot either into the corresponding operating systems for Interlisp, Smalltalk or Mesa. https://en.wikipedia.org/wiki/Xerox_Star https://en.wikipedia.org/wiki/Xerox_Star Similar for the MIT CADR and some others, it was also a microprogrammed 32bit CPU. Symbolics' CPU were also microprogrammed, but they added hardware features to it. The SPUR (which is a RISC chip) mentioned is a more generic design, but with support for languages features for Lisp. There were other chips in the making at that time, like the Symbolics Sunstone CPU, which was also a RISC design for Lisp, but which also did not reach the market. > Take Java for an example: it's possible to implement the JVM as a chip, but then you have a stack machine, and you can't JIT it onto a register architecture. One could do that, but it would be a more complex chip. For Lisp CPUS "fast" for benchmarks was also not that much a goal. Goals oftenwere "fast" execution of a Lisp operating system (written in a dynamically typed and garbage collected language), support for large address spaces, support for Lisp data types&data representation, generic operations (like generic arithmetic operations) and compact machine code.