4 ms·
ZeroPoint's nanosecond-scale memory compression could tame power-hungry AI infra
- jmakov 2y agoSounds like ZRAM implemented in HW
- smarm52 2y agoThey don't cite a paper to show how it works, but if the graphic is something they came up with, then I'm skeptical. The graphic indicates they pack the memory more efficiently, which is a solution to the packing problem, which is notoriously difficult to do optimally. https://en.wikipedia.org/wiki/Packing_problems https://en.wikipedia.org/wiki/Packing_problems ---- EDIT: Checking their CTO (Angelos Arelakis [1]), they do a lot of work on compression [2]. Their most cited paper seems a lot like what they talk about in the article: Arelakis, A., & Stenstrom, P. (2014). SC2: A statistical compression cache scheme. ACM SIGARCH Computer Architecture News, 42(3), 145-156. Checking Sci-Hub, the paper is about a cache device that uses "Huffman-coding" [3] for performance improvements at the memory level. Which seems interesting, but it's a statistical cache, and so the ~50% savings they talk about in the article is probably the average case, rather than some super-revolutionary "perfect" system. [1] https://www.crunchbase.com/person/angelos-arelakis https://www.crunchbase.com/person/angelos-arelakis [2] https://scholar.google.com/citations?hl=en&user=8uWjQC0AAAAJ&view_op=list_works https://scholar.google.com/citations?hl=en&user=8uWjQC0AAAAJ... [3] https://en.wikipedia.org/wiki/Huffman_coding https://en.wikipedia.org/wiki/Huffman_coding