1. Do smaller factories typically use pre-fabricated <100> p-wafers with a FET gate-layer for CMOS? 2. Also, is it normal to see circular thickness defects ove

1. Do smaller factories typically use pre-fabricated <100> p-wafers with a FET gate-layer for CMOS? 2. Also, is it normal to see circular thickness defects over +-200nm where a wafer vacuum-chuck was obviously set during double-sided polishing? The deformed synthetic sapphire wafers are ruining my fun. Thanks in advance, =)