3 ms·
So I think if I'm reading it right, it means there's 1x NVDEC chips. Each chip is capable of handling multiple encodings / decodings, as each of the transcoding
by burningion 2y ago
So I think if I'm reading it right, it means there's 1x NVDEC chips. Each chip is capable of handling multiple encodings / decodings, as each of the transcodings list means concurrent streams of NVDEC -> NVENC.