3 ms·

Is there really a point to making gates even smaller when the leakage is already so atrocious? The future of Moore's law is in whoever finds a way to make a mod

Is there really a point to making gates even smaller when the leakage is already so atrocious? The future of Moore's law is in whoever finds a way to make a modern PC that doesn't pull a god damn kilowatt.

fregonics 2y ago
Those are two different problems. And this is just research for now. But to address leakage there are already the gate-all-around transistors [1], which are in semiconductor companies roadmaps [2]. [1] https://www.asml.com/en/news/stories/2022/what-is-a-gate-all-around-transistor https://www.asml.com/en/news/stories/2022/what-is-a-gate-all... [2] https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros/3 https://www.anandtech.com/show/16823/intel-accelerated-offen...
- adgjlsfhk1 2y ago
  Also backside power delivery supposedly helps a lot by letting you use bigger (so lower resistance) wires.
sapiogram 2y ago
As long as overall power consumption keeps decreasing, yes.
ThrowawayTestr 2y ago
I disagree. The future of Moore's law is whoever finds a way to cool a kilowatt cpu effectively.
- tonetegeatinst 2y ago
  I agree with you in a lot of aspects. Obviously extreme hyper NA EUV is possible....and with Wakefield accelerators we might be able to shrink the size of these machines to a more feasible size. And the gate all around transistor seems like its how the industry plans on handling leakiness when shrinking the size of our circuits.....yet cooling is the largest issue we face in some ways. Noctua and gamers nexus have shown just how competitive the air cooler market is for cooler performance....and how the CPU package deforms over time impacts cooling. Personally, I think we could make CPUs that are much bigger and stack the transistors and chips even higher if we managed to get the cooling figured out. Imagine a 3d tower of a CPU where cooling channels exist in between layers # = your silicon chip @ = a cooling channel Now imagine stacking like the following ###### @@@@@ ###### @@@@@ ###### @@@@@ ###### This could be a starting point for stacking chips.....sort of like how 3d nand is stacked....yet instead we stack the CPU wafers and have cooling channels in between them. You could even make the CPU and cooler, and have the chip interconnect going up the sides.....
mensetmanusman 2y ago
Moore’s law per power died a while ago, cost per transistor before that, but the speed advantage of waiting 10 or 100 times less is still attractive.
- luyu_wu 2y ago
  This is Dennard's scaling.
Cthulhu_ 2y ago
Is that down to leakage or the sheer amount of transistors / work being done?

fregonics 2y ago

Those are two different problems. And this is just research for now. But to address leakage there are already the gate-all-around transistors [1], which are in semiconductor companies roadmaps [2]. [1] https://www.asml.com/en/news/stories/2022/what-is-a-gate-all-around-transistor https://www.asml.com/en/news/stories/2022/what-is-a-gate-all... [2] https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros/3 https://www.anandtech.com/show/16823/intel-accelerated-offen...

adgjlsfhk1 2y ago
Also backside power delivery supposedly helps a lot by letting you use bigger (so lower resistance) wires.

sapiogram 2y ago

As long as overall power consumption keeps decreasing, yes.

ThrowawayTestr 2y ago

I disagree. The future of Moore's law is whoever finds a way to cool a kilowatt cpu effectively.

tonetegeatinst 2y ago
I agree with you in a lot of aspects. Obviously extreme hyper NA EUV is possible....and with Wakefield accelerators we might be able to shrink the size of these machines to a more feasible size. And the gate all around transistor seems like its how the industry plans on handling leakiness when shrinking the size of our circuits.....yet cooling is the largest issue we face in some ways. Noctua and gamers nexus have shown just how competitive the air cooler market is for cooler performance....and how the CPU package deforms over time impacts cooling. Personally, I think we could make CPUs that are much bigger and stack the transistors and chips even higher if we managed to get the cooling figured out. Imagine a 3d tower of a CPU where cooling channels exist in between layers # = your silicon chip @ = a cooling channel Now imagine stacking like the following ###### @@@@@ ###### @@@@@ ###### @@@@@ ###### This could be a starting point for stacking chips.....sort of like how 3d nand is stacked....yet instead we stack the CPU wafers and have cooling channels in between them. You could even make the CPU and cooler, and have the chip interconnect going up the sides.....

mensetmanusman 2y ago

Moore’s law per power died a while ago, cost per transistor before that, but the speed advantage of waiting 10 or 100 times less is still attractive.

luyu_wu 2y ago
This is Dennard's scaling.

Cthulhu_ 2y ago

Is that down to leakage or the sheer amount of transistors / work being done?