4 ms·

Is the Future of Moore's Law in a Particle Accelerator?

42 points by elashri 2y ago

moffkalast 2y ago
Is there really a point to making gates even smaller when the leakage is already so atrocious? The future of Moore's law is in whoever finds a way to make a modern PC that doesn't pull a god damn kilowatt.
- fregonics 2y ago
  Those are two different problems. And this is just research for now. But to address leakage there are already the gate-all-around transistors [1], which are in semiconductor companies roadmaps [2]. [1] https://www.asml.com/en/news/stories/2022/what-is-a-gate-all-around-transistor https://www.asml.com/en/news/stories/2022/what-is-a-gate-all... [2] https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros/3 https://www.anandtech.com/show/16823/intel-accelerated-offen...
  - adgjlsfhk1 2y ago
    Also backside power delivery supposedly helps a lot by letting you use bigger (so lower resistance) wires.
- sapiogram 2y ago
  As long as overall power consumption keeps decreasing, yes.
- ThrowawayTestr 2y ago
  I disagree. The future of Moore's law is whoever finds a way to cool a kilowatt cpu effectively.
  - tonetegeatinst 2y ago
    I agree with you in a lot of aspects. Obviously extreme hyper NA EUV is possible....and with Wakefield accelerators we might be able to shrink the size of these machines to a more feasible size. And the gate all around transistor seems like its how the industry plans on handling leakiness when shrinking the size of our circuits.....yet cooling is the largest issue we face in some ways. Noctua and gamers nexus have shown just how competitive the air cooler market is for cooler performance....and how the CPU package deforms over time impacts cooling. Personally, I think we could make CPUs that are much bigger and stack the transistors and chips even higher if we managed to get the cooling figured out. Imagine a 3d tower of a CPU where cooling channels exist in between layers # = your silicon chip @ = a cooling channel Now imagine stacking like the following ###### @@@@@ ###### @@@@@ ###### @@@@@ ###### This could be a starting point for stacking chips.....sort of like how 3d nand is stacked....yet instead we stack the CPU wafers and have cooling channels in between them. You could even make the CPU and cooler, and have the chip interconnect going up the sides.....
- mensetmanusman 2y ago
  Moore’s law per power died a while ago, cost per transistor before that, but the speed advantage of waiting 10 or 100 times less is still attractive.
  - luyu_wu 2y ago
    This is Dennard's scaling.
- Cthulhu_ 2y ago
  Is that down to leakage or the sheer amount of transistors / work being done?
amirhirsch 2y ago
Laser wakefield accelerators should help with miniaturization of the particle accelerators needed for free electron lasers. It seems like to get the beam energy levels required for a FEL we need methods for staging wakefield accelerators. Staging has been demonstrated but perhaps not scaled up in beam energy? It’s been a few years since I’ve checked in on this domain…
- afp 2y ago
  It is already possible to reach 800 MeV (the energy for an EUV FEL according to the article) with single-stage laser wakefield accelerators. The problem is doing so with sufficient beam quality, reproducibility and repetition rate. The energy efficiency would also be a problem, as it is nowhere close to what an energy recovery linac could achieve.
  - amirhirsch 2y ago
    I'm not an expert in this domain and I really wish I could understand more of the issues on efficiency--it still seems like there are major engineering gaps preventing a table-top FEL from existing. I know a little about beam quality issues, but don't really have any sense for the power scales and efficiencies. Are we talking like 10x more power for the same EUV beam from Laser plasma accelerators over an energy recovery linac or an ASML unit? If the repetition rate is too low, is it possible to re-use an electron beam and use mutliple undulators for multiple EUV beams with separate lithographic reticles? Is it the chirped-pulse-amplified lasers that have slow rep rate or is it possible to have a single driving laser with multiple plasma targets? Is there a way it becomes viable if you can make something that is dramatically lower in cost even if it burns 10x the power?
    - afp 2y ago
      The issue with the efficiency begins already with the high-power lasers that are needed for wakefield acceleration, which have a typical wall-plug efficiency of ~0.1%. From that, only about ~1% of the laser pulse energy gets transferred into the accelerated electron beam. And only about ~0.1% of that gets converted into light again during the FEL process. All together, that would mean an efficiency of ~10^{-8}, which is about a million times smaller than for the ERL (I'm no expert there, but I think in the article they mention 1-10% efficiency). There are prospects for much more efficient high-power lasers, but there's still a long way to go. I don't know what would dominate the costs in this particular case, but given the low efficiency and reliability (high-power lasers break often) as well as the other issues, I wouldn't bet on wakefield accelerators as an alternative.
superposeur 2y ago
Extremely small wavelengths can be achieved using beams of electrons in place of beams of photons, as in Scanning Tunneling Microscopes and electron diffraction. Do you know if there is any thought of developing “electron beam lithography”, where an electron beam would etch the pattern on silicon and not merely be used as a source of secondary photons?
- stanleykm 2y ago
  As I understand it electron beam lithography exists as a technology (and is maybe used for reticles? not sure) but the throughput is way too low for production. Its several orders of magnitude slower than euv apparently.
  - superposeur 2y ago
    Interesting. With all the mega bucks and efforts to produce smaller wavelength photon beams, I wonder if a comparable investment would increase throughput? Or maybe there is an insurmountable technical hurdle.
    - adgjlsfhk1 2y ago
      The problem is pretty fundamental. Optical approaches illuminate the whole chip at once. Electron beams have to go transistor by transistor.
      - AnimalMuppet 2y ago
        Why? What prevents you from illuminating the whole chip with electrons? Can't get an electron source "bright" enough? Uniform enough? The chip can't handle that much current? Or what?
        adgjlsfhk1 2y ago
        The problem is that you can't make mirrors or lenses for electrons, so the mask can't be bigger than the chip. There's also the significant problem that shooting electrons at things tends to damage them, so making a mask that can survive the process sounds very tricky.
ETHisso2017 2y ago
No mention of the SSMB project? AFAIK that one is further along than the EUV-FEL approach
deleted 2y ago
[deleted]
foundart 2y ago
For background, there’s a great write up of current approaches at https://spectrum.ieee.org/high-na-euv https://spectrum.ieee.org/high-na-euv

42 points by elashri 2y ago

Is there really a point to making gates even smaller when the leakage is already so atrocious? The future of Moore's law is in whoever finds a way to make a modern PC that doesn't pull a god damn kilowatt.

fregonics 2y ago
Those are two different problems. And this is just research for now. But to address leakage there are already the gate-all-around transistors [1], which are in semiconductor companies roadmaps [2]. [1] https://www.asml.com/en/news/stories/2022/what-is-a-gate-all-around-transistor https://www.asml.com/en/news/stories/2022/what-is-a-gate-all... [2] https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros/3 https://www.anandtech.com/show/16823/intel-accelerated-offen...
- adgjlsfhk1 2y ago
  Also backside power delivery supposedly helps a lot by letting you use bigger (so lower resistance) wires.
sapiogram 2y ago
As long as overall power consumption keeps decreasing, yes.
ThrowawayTestr 2y ago
I disagree. The future of Moore's law is whoever finds a way to cool a kilowatt cpu effectively.
- tonetegeatinst 2y ago
  I agree with you in a lot of aspects. Obviously extreme hyper NA EUV is possible....and with Wakefield accelerators we might be able to shrink the size of these machines to a more feasible size. And the gate all around transistor seems like its how the industry plans on handling leakiness when shrinking the size of our circuits.....yet cooling is the largest issue we face in some ways. Noctua and gamers nexus have shown just how competitive the air cooler market is for cooler performance....and how the CPU package deforms over time impacts cooling. Personally, I think we could make CPUs that are much bigger and stack the transistors and chips even higher if we managed to get the cooling figured out. Imagine a 3d tower of a CPU where cooling channels exist in between layers # = your silicon chip @ = a cooling channel Now imagine stacking like the following ###### @@@@@ ###### @@@@@ ###### @@@@@ ###### This could be a starting point for stacking chips.....sort of like how 3d nand is stacked....yet instead we stack the CPU wafers and have cooling channels in between them. You could even make the CPU and cooler, and have the chip interconnect going up the sides.....
mensetmanusman 2y ago
Moore’s law per power died a while ago, cost per transistor before that, but the speed advantage of waiting 10 or 100 times less is still attractive.
- luyu_wu 2y ago
  This is Dennard's scaling.
Cthulhu_ 2y ago
Is that down to leakage or the sheer amount of transistors / work being done?

amirhirsch 2y ago

Laser wakefield accelerators should help with miniaturization of the particle accelerators needed for free electron lasers. It seems like to get the beam energy levels required for a FEL we need methods for staging wakefield accelerators. Staging has been demonstrated but perhaps not scaled up in beam energy? It’s been a few years since I’ve checked in on this domain…

afp 2y ago
It is already possible to reach 800 MeV (the energy for an EUV FEL according to the article) with single-stage laser wakefield accelerators. The problem is doing so with sufficient beam quality, reproducibility and repetition rate. The energy efficiency would also be a problem, as it is nowhere close to what an energy recovery linac could achieve.
- amirhirsch 2y ago
  I'm not an expert in this domain and I really wish I could understand more of the issues on efficiency--it still seems like there are major engineering gaps preventing a table-top FEL from existing. I know a little about beam quality issues, but don't really have any sense for the power scales and efficiencies. Are we talking like 10x more power for the same EUV beam from Laser plasma accelerators over an energy recovery linac or an ASML unit? If the repetition rate is too low, is it possible to re-use an electron beam and use mutliple undulators for multiple EUV beams with separate lithographic reticles? Is it the chirped-pulse-amplified lasers that have slow rep rate or is it possible to have a single driving laser with multiple plasma targets? Is there a way it becomes viable if you can make something that is dramatically lower in cost even if it burns 10x the power?
  - afp 2y ago
    The issue with the efficiency begins already with the high-power lasers that are needed for wakefield acceleration, which have a typical wall-plug efficiency of ~0.1%. From that, only about ~1% of the laser pulse energy gets transferred into the accelerated electron beam. And only about ~0.1% of that gets converted into light again during the FEL process. All together, that would mean an efficiency of ~10^{-8}, which is about a million times smaller than for the ERL (I'm no expert there, but I think in the article they mention 1-10% efficiency). There are prospects for much more efficient high-power lasers, but there's still a long way to go. I don't know what would dominate the costs in this particular case, but given the low efficiency and reliability (high-power lasers break often) as well as the other issues, I wouldn't bet on wakefield accelerators as an alternative.

superposeur 2y ago

Extremely small wavelengths can be achieved using beams of electrons in place of beams of photons, as in Scanning Tunneling Microscopes and electron diffraction. Do you know if there is any thought of developing “electron beam lithography”, where an electron beam would etch the pattern on silicon and not merely be used as a source of secondary photons?

stanleykm 2y ago
As I understand it electron beam lithography exists as a technology (and is maybe used for reticles? not sure) but the throughput is way too low for production. Its several orders of magnitude slower than euv apparently.
- superposeur 2y ago
  Interesting. With all the mega bucks and efforts to produce smaller wavelength photon beams, I wonder if a comparable investment would increase throughput? Or maybe there is an insurmountable technical hurdle.
  - adgjlsfhk1 2y ago
    The problem is pretty fundamental. Optical approaches illuminate the whole chip at once. Electron beams have to go transistor by transistor.
    - AnimalMuppet 2y ago
      Why? What prevents you from illuminating the whole chip with electrons? Can't get an electron source "bright" enough? Uniform enough? The chip can't handle that much current? Or what?
      - adgjlsfhk1 2y ago
        The problem is that you can't make mirrors or lenses for electrons, so the mask can't be bigger than the chip. There's also the significant problem that shooting electrons at things tends to damage them, so making a mask that can survive the process sounds very tricky.

ETHisso2017 2y ago

No mention of the SSMB project? AFAIK that one is further along than the EUV-FEL approach

deleted 2y ago

[deleted]

foundart 2y ago

For background, there’s a great write up of current approaches at https://spectrum.ieee.org/high-na-euv https://spectrum.ieee.org/high-na-euv