3 ms·

The PIOs really are a superpower for this kind of thing. Interestingly the RP2040 documentation mentions that each PIO uses roughly the same silicon area as a d

The PIOs really are a superpower for this kind of thing. Interestingly the RP2040 documentation mentions that each PIO uses roughly the same silicon area as a dedicated peripheral for something like SPI or I2C, so now that the concept has been proven to work in practice it would be amazing if the successor chip ditched most of the single-purpose I/O peripherals and replaced them with a huge battery of PIO channels which can each be programmed to do SPI, I2C, or whatever else as needed.

_Microft 2y ago
Here's a quote from Eben Upton (CEO of Raspberry Pi Trading, 2023): “We know what people don’t like about [RP]2040,” Upton admitted at the event, “the [Arm Cortex-]M0+ [architecture], could have more RAM, could have more GPIO [General-Purpose Input/Output], and we know what people do like — the PIO [Programmable Input/Output blocks]… and we have a chip team.”, [0][1] That doesn't sound too bad, hmm? [0] https://blog.adafruit.com/2023/12/04/raspberry-pi-hints-at-new-products-in-2024-raspberrypi-hacksterio/ https://blog.adafruit.com/2023/12/04/raspberry-pi-hints-at-n... [1] https://www.hackster.io/news/eben-upton-hints-at-an-rp2040-successor-promises-a-raspberry-pi-compute-module-5-in-2024-ec331994aca3 https://www.hackster.io/news/eben-upton-hints-at-an-rp2040-s...
- jsheard 2y ago
  Sounds good to me. The decision to go for two tiny cores rather than one beefier core with an FPU was strange, and it would be nice to have a PSRAM interface like the ESP32s do. They seem to want to have one chip SKU which does everything rather than a million variants, hence why they made the flash external on the RP2040, so if they can extend that to one chip which can be configured with variable flash size, memory size, and has tons of PIOs...
  - deleted 2y ago
    [deleted]
  - phire 2y ago
    > The decision to go for two tiny cores rather than one beefier core with an FPU was strange It's very useful to dedicate an entire core to running your timing-critical assembly code, and only run higher level non timing critical application code on the other core.

_Microft 2y ago

Here's a quote from Eben Upton (CEO of Raspberry Pi Trading, 2023): “We know what people don’t like about [RP]2040,” Upton admitted at the event, “the [Arm Cortex-]M0+ [architecture], could have more RAM, could have more GPIO [General-Purpose Input/Output], and we know what people do like — the PIO [Programmable Input/Output blocks]… and we have a chip team.”, [0][1] That doesn't sound too bad, hmm? [0] https://blog.adafruit.com/2023/12/04/raspberry-pi-hints-at-new-products-in-2024-raspberrypi-hacksterio/ https://blog.adafruit.com/2023/12/04/raspberry-pi-hints-at-n... [1] https://www.hackster.io/news/eben-upton-hints-at-an-rp2040-successor-promises-a-raspberry-pi-compute-module-5-in-2024-ec331994aca3 https://www.hackster.io/news/eben-upton-hints-at-an-rp2040-s...

jsheard 2y ago
Sounds good to me. The decision to go for two tiny cores rather than one beefier core with an FPU was strange, and it would be nice to have a PSRAM interface like the ESP32s do. They seem to want to have one chip SKU which does everything rather than a million variants, hence why they made the flash external on the RP2040, so if they can extend that to one chip which can be configured with variable flash size, memory size, and has tons of PIOs...
- deleted 2y ago
  [deleted]
- phire 2y ago
  > The decision to go for two tiny cores rather than one beefier core with an FPU was strange It's very useful to dedicate an entire core to running your timing-critical assembly code, and only run higher level non timing critical application code on the other core.