3 ms·
On x86, the shift instruction only looks at the bottom 5 bits of the shift distance. x<<32 effectively is interpreted as x<<0. (I'm sure other architectures hav
by pdw 14y ago
On x86, the shift instruction only looks at the bottom 5 bits of the shift distance. x<<32 effectively is interpreted as x<<0. (I'm sure other architectures have the same restriction.)
- astrange 14y agoDifferent architectures use different numbers of bits. I think PPC uses 4 but I can't remember how to check this at the moment.
- nitrogen 14y agoDoes that imply that PPC is limited to shifting at most 15 bits at a time?
- astrange 14y agoIn fact the answer was 5 bits for 32bit and 7 bits for 64bit[1]. x86-64 uses 5 bits for 32bit and for 64bit (shld/shrd can't shift more than 31 bits). 7 bits is problematic because some code may assume that x << -y is an optimization for x << (32-y). I thought there was some architecture where this assumption didn't work on 32bit either, which led to my post above. [1] http://pic.dhe.ibm.com/infocenter/aix/v7r1/topic/com.ibm.aix.aixassem/doc/alangref/alangref.pdf http://pic.dhe.ibm.com/infocenter/aix/v7r1/topic/com.ibm.aix...