This whole tech is mostly to solve problem of die defects. When die size increases, output decreases very much. One (really frequently used) solution, to make d

This whole tech is mostly to solve problem of die defects. When die size increases, output decreases very much. One (really frequently used) solution, to make design from few separate chips on one physical die and then disable part of die with jumpers (and reconfigure working parts with jumpers). For example, many DDR-3 chips have 6 chips on one die, but only 2..4 enabled after finish testing. But if one could cheaply construct 2.5D, placing tested chiplets on silicon imposer, this create whole new fabrication opportunities. For example, in newest Intel chips, could be one high-performance core (i7) + few Atom cores + HBM high-speed DRAM and even some high power current switch or analog die. Looks like, in nearest decade we will see single chip smartphones, etc.