3 ms·

These connections are big compared to other features - that means more capacitance (but far less than pins and PCB traces) that means that you are not going to

These connections are big compared to other features - that means more capacitance (but far less than pins and PCB traces) that means that you are not going to be building designs where there's a design block moves into 3D more it's for connecting logical blocks together (CPU's L1 to L2/L3 to memory) the sorts of places where you can spend a clock to move data between layers. As other's have mentioned dealing with heat is an issue too - all those insulating layers don't conduct heat well either - 3D chips tend to the "hairy smoking golfball" scenario where getting rid of heat becomes your biggest problem

rbanffy 2y ago
Since the interposer traffic is mostly vertical, you could add horizontal tracks of metal to conduct some heat out. Limited, but better than nothing. I wonder how small a Stirling engine can be and power microfluidic cooling inside one such interposer. What I really like about this is that the buses can be very wide, so even if you spend one clock cycle to do something, that something can be quite a lot of small things.
ChoGGi 2y ago
I wonder if we'll get little tiny heat pipes or "solid state" fans embedded inside chips, be nice to use some of that extra heatsink block.
- wmf 2y ago
  IBM Zurich did some work on etching microchannels into dies for water cooling.
- kvemkon 2y ago
  This reminded me of a so called "micro-vibration ventilator" https://www.pcworld.com/article/1388332/new-airjet-chips-can-double-a-laptops-performance.html https://www.pcworld.com/article/1388332/new-airjet-chips-can...
petra 2y ago
To solve the heat issue let's limit ourselves to 2.5D chips, since the bottom layer barely heats. Die size:350mm2,millions of connections per mm2, meaning 350 million connections @1ghz - 350,000 tbit/sec of memory bandwidth. The realistic number Will probably be much lower, but still, even 2.5D could solve the memory wall.
simne 2y ago
This whole tech is mostly to solve problem of die defects. When die size increases, output decreases very much. One (really frequently used) solution, to make design from few separate chips on one physical die and then disable part of die with jumpers (and reconfigure working parts with jumpers). For example, many DDR-3 chips have 6 chips on one die, but only 2..4 enabled after finish testing. But if one could cheaply construct 2.5D, placing tested chiplets on silicon imposer, this create whole new fabrication opportunities. For example, in newest Intel chips, could be one high-performance core (i7) + few Atom cores + HBM high-speed DRAM and even some high power current switch or analog die. Looks like, in nearest decade we will see single chip smartphones, etc.

rbanffy 2y ago

Since the interposer traffic is mostly vertical, you could add horizontal tracks of metal to conduct some heat out. Limited, but better than nothing. I wonder how small a Stirling engine can be and power microfluidic cooling inside one such interposer. What I really like about this is that the buses can be very wide, so even if you spend one clock cycle to do something, that something can be quite a lot of small things.

ChoGGi 2y ago

I wonder if we'll get little tiny heat pipes or "solid state" fans embedded inside chips, be nice to use some of that extra heatsink block.

wmf 2y ago
IBM Zurich did some work on etching microchannels into dies for water cooling.
kvemkon 2y ago
This reminded me of a so called "micro-vibration ventilator" https://www.pcworld.com/article/1388332/new-airjet-chips-can-double-a-laptops-performance.html https://www.pcworld.com/article/1388332/new-airjet-chips-can...

petra 2y ago

To solve the heat issue let's limit ourselves to 2.5D chips, since the bottom layer barely heats. Die size:350mm2,millions of connections per mm2, meaning 350 million connections @1ghz - 350,000 tbit/sec of memory bandwidth. The realistic number Will probably be much lower, but still, even 2.5D could solve the memory wall.

simne 2y ago

This whole tech is mostly to solve problem of die defects. When die size increases, output decreases very much. One (really frequently used) solution, to make design from few separate chips on one physical die and then disable part of die with jumpers (and reconfigure working parts with jumpers). For example, many DDR-3 chips have 6 chips on one die, but only 2..4 enabled after finish testing. But if one could cheaply construct 2.5D, placing tested chiplets on silicon imposer, this create whole new fabrication opportunities. For example, in newest Intel chips, could be one high-performance core (i7) + few Atom cores + HBM high-speed DRAM and even some high power current switch or analog die. Looks like, in nearest decade we will see single chip smartphones, etc.