I think the current version of their 3D cache does now extend over the cores and not just the cache of the underlying die. The other big factor is that their c

I think the current version of their 3D cache does now extend over the cores and not just the cache of the underlying die. The other big factor is that their cache chiplets are built with a fab process and standard cells that cannot tolerate high voltages, so the cores (which are on the same power rail) are constrained to not operate at the extreme end of the voltage/frequency curve where high-end desktop processors sacrifice everything to win a benchmark.