I used to think this too, but apparently RISC isn't about the number of instructions, but the complexity or execution time of each; as https://en.wikipedia.org/

I used to think this too, but apparently RISC isn't about the number of instructions, but the complexity or execution time of each; as https://en.wikipedia.org/wiki/Reduced_instruction_set_computer https://en.wikipedia.org/wiki/Reduced_instruction_set_comput... puts it, > The key operational concept of the RISC computer is that each instruction performs only one function (e.g. copy a value from memory to a register). and in fact that page even mentions at https://en.wikipedia.org/wiki/Reduced_instruction_set_computer#Comparison_to_other_architectures https://en.wikipedia.org/wiki/Reduced_instruction_set_comput... that > Some CPUs have been specifically designed to have a very small set of instructions—but these designs are very different from classic RISC designs, so they have been given other names such as minimal instruction set computer (MISC) or transport triggered architecture (TTA).