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Amazing that you can look at an ISA like ARM and say "reduced instruction set". It has 1300+ opcodes.
by jeffbee 2y ago
Amazing that you can look at an ISA like ARM and say "reduced instruction set". It has 1300+ opcodes.
- mhh__ 2y agoAt best ARM is regular rather than reduced
- JonChesterfield 2y agoAarch64 looks a lot like x86-64 to me. Deep pipelines, loads of silicon spent on branch prediction, vector units.
- aidenn0 2y agoIt seems that "RISC" has just become a synonym for "load-store architecture" Non-embedded POWER implementations are around 1000 opcodes, depending on the features supported, and even MIPS eventually got a square-root instruction.
- yjftsjthsd-h 2y agoI used to think this too, but apparently RISC isn't about the number of instructions, but the complexity or execution time of each; as https://en.wikipedia.org/wiki/Reduced_instruction_set_computer https://en.wikipedia.org/wiki/Reduced_instruction_set_comput... puts it, > The key operational concept of the RISC computer is that each instruction performs only one function (e.g. copy a value from memory to a register). and in fact that page even mentions at https://en.wikipedia.org/wiki/Reduced_instruction_set_computer#Comparison_to_other_architectures https://en.wikipedia.org/wiki/Reduced_instruction_set_comput... that > Some CPUs have been specifically designed to have a very small set of instructions—but these designs are very different from classic RISC designs, so they have been given other names such as minimal instruction set computer (MISC) or transport triggered architecture (TTA).