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And the main question: Is it overall better (faster and less power hungry) than a reduced instruction set, powerful laptop ARM based CPU which is around the cor

And the main question: Is it overall better (faster and less power hungry) than a reduced instruction set, powerful laptop ARM based CPU which is around the corner (Qualcomm)? Guessing not...

Rinzler89 2y ago
There's still an insurmountable amount of apps that are still X86 exclusive both new and legacy. So the chip not beating the best of ARM in benchmarks is largely irelevant. A Ferrari will beat a tractor on every test bench numbers and every track, but I can't plow the field with a Ferrari, so any improvements in tractor technology is still welcome despite they'll never beat Ferraris.
- hajile 2y ago
  I hear this argument, but I don't really believe it. If you're talking apps before say 2015 (10 years ago), they can be emulated on ARM faster than they ran natively. That rules out 95% of the backward compatibility argument. Most more recent apps are very portable. They were written in a managed language running on a cross-platform runtime. The source code is likely stored in git so it can be tracked down and recompiled. Over 15 years of modern smartphones has ensured that most low-level libraries have support for ARM and other ISAs too as being ISA-agnostic has once again become important. Apple's 4 years of transition aren't to be underestimated either. Lots of devs/creatives use ARM machines and have ensured that pretty much all of the biggest pro software runs very well on non-x86 platforms. Yes, some stuff remains, but I don't think the remaining stuff is as big a deal as some people claim.
jeffbee 2y ago
Amazing that you can look at an ISA like ARM and say "reduced instruction set". It has 1300+ opcodes.
- mhh__ 2y ago
  At best ARM is regular rather than reduced
- JonChesterfield 2y ago
  Aarch64 looks a lot like x86-64 to me. Deep pipelines, loads of silicon spent on branch prediction, vector units.
- aidenn0 2y ago
  It seems that "RISC" has just become a synonym for "load-store architecture" Non-embedded POWER implementations are around 1000 opcodes, depending on the features supported, and even MIPS eventually got a square-root instruction.
- yjftsjthsd-h 2y ago
  I used to think this too, but apparently RISC isn't about the number of instructions, but the complexity or execution time of each; as https://en.wikipedia.org/wiki/Reduced_instruction_set_computer https://en.wikipedia.org/wiki/Reduced_instruction_set_comput... puts it, > The key operational concept of the RISC computer is that each instruction performs only one function (e.g. copy a value from memory to a register). and in fact that page even mentions at https://en.wikipedia.org/wiki/Reduced_instruction_set_computer#Comparison_to_other_architectures https://en.wikipedia.org/wiki/Reduced_instruction_set_comput... that > Some CPUs have been specifically designed to have a very small set of instructions—but these designs are very different from classic RISC designs, so they have been given other names such as minimal instruction set computer (MISC) or transport triggered architecture (TTA).
ffgjgf1 2y ago
IIRC they claimed that it supposedly is
- therealmarv 2y ago
  Would be great if true! Competition always good for us consumers.
yjftsjthsd-h 2y ago
What are you guessing from? Historically, generation for generation, x86 is good at performance and awful at power consumption. Even when Apple (not aarch64 in general, just Apple) briefly pulled ahead on both, subsequent x86 chips kept winning on raw performance, even as they got destroyed on perf per Watt.
- dur-randir 2y ago
  >kept winning on raw performance 13900K lost couple of % in single tread performance, which lead to 14900K being so overclocked/overvolted that it lead to it being useless for what it's made for - crunching numbers. See https://www.radgametools.com/oodleintel.htm https://www.radgametools.com/oodleintel.htm.

And the main question: Is it overall better (faster and less power hungry) than a reduced instruction set, powerful laptop ARM based CPU which is around the corner (Qualcomm)? Guessing not...

Rinzler89 2y ago

There's still an insurmountable amount of apps that are still X86 exclusive both new and legacy. So the chip not beating the best of ARM in benchmarks is largely irelevant. A Ferrari will beat a tractor on every test bench numbers and every track, but I can't plow the field with a Ferrari, so any improvements in tractor technology is still welcome despite they'll never beat Ferraris.

hajile 2y ago
I hear this argument, but I don't really believe it. If you're talking apps before say 2015 (10 years ago), they can be emulated on ARM faster than they ran natively. That rules out 95% of the backward compatibility argument. Most more recent apps are very portable. They were written in a managed language running on a cross-platform runtime. The source code is likely stored in git so it can be tracked down and recompiled. Over 15 years of modern smartphones has ensured that most low-level libraries have support for ARM and other ISAs too as being ISA-agnostic has once again become important. Apple's 4 years of transition aren't to be underestimated either. Lots of devs/creatives use ARM machines and have ensured that pretty much all of the biggest pro software runs very well on non-x86 platforms. Yes, some stuff remains, but I don't think the remaining stuff is as big a deal as some people claim.

jeffbee 2y ago

Amazing that you can look at an ISA like ARM and say "reduced instruction set". It has 1300+ opcodes.

mhh__ 2y ago
At best ARM is regular rather than reduced
JonChesterfield 2y ago
Aarch64 looks a lot like x86-64 to me. Deep pipelines, loads of silicon spent on branch prediction, vector units.
aidenn0 2y ago
It seems that "RISC" has just become a synonym for "load-store architecture" Non-embedded POWER implementations are around 1000 opcodes, depending on the features supported, and even MIPS eventually got a square-root instruction.
yjftsjthsd-h 2y ago
I used to think this too, but apparently RISC isn't about the number of instructions, but the complexity or execution time of each; as https://en.wikipedia.org/wiki/Reduced_instruction_set_computer https://en.wikipedia.org/wiki/Reduced_instruction_set_comput... puts it, > The key operational concept of the RISC computer is that each instruction performs only one function (e.g. copy a value from memory to a register). and in fact that page even mentions at https://en.wikipedia.org/wiki/Reduced_instruction_set_computer#Comparison_to_other_architectures https://en.wikipedia.org/wiki/Reduced_instruction_set_comput... that > Some CPUs have been specifically designed to have a very small set of instructions—but these designs are very different from classic RISC designs, so they have been given other names such as minimal instruction set computer (MISC) or transport triggered architecture (TTA).

ffgjgf1 2y ago

IIRC they claimed that it supposedly is

therealmarv 2y ago
Would be great if true! Competition always good for us consumers.

yjftsjthsd-h 2y ago

What are you guessing from? Historically, generation for generation, x86 is good at performance and awful at power consumption. Even when Apple (not aarch64 in general, just Apple) briefly pulled ahead on both, subsequent x86 chips kept winning on raw performance, even as they got destroyed on perf per Watt.

dur-randir 2y ago
>kept winning on raw performance 13900K lost couple of % in single tread performance, which lead to 14900K being so overclocked/overvolted that it lead to it being useless for what it's made for - crunching numbers. See https://www.radgametools.com/oodleintel.htm https://www.radgametools.com/oodleintel.htm.