4 ms·
Well back in the P6 to Conroe timespan we had that detour for more Ghz with P4 that turned out badly where probably assumed wider issue wouldn't be an issue whe
by whizzter 2y ago
Well back in the P6 to Conroe timespan we had that detour for more Ghz with P4 that turned out badly where probably assumed wider issue wouldn't be an issue when you increased the clockrate.
Also back in those days 32bit x86 with it's anemic 8 GP registers (and stack-based-fpu) it was hard to avoid any dependencies w/o trying to calculate memory positions, nowadays we have 64bit x86 with 16 GP registers and separated FPU XMM registers (compilers can leave much more in memory and registers are probably far easier to do dependency resolution on).
Oh and a theory could be that JS,Java,C#,Rust,etc code with lots of non-taken safety barriers(out of bounds, type-tests,etc) has probably been analyzed and been found to be a prime candidate for parallell issue.