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At the moment I am wondering if I could build an accelerator for george hotz' tinygrad[1] with cheap FPGAs (i do have an arty a7 35K, this might be too small, i

At the moment I am wondering if I could build an accelerator for george hotz' tinygrad[1] with cheap FPGAs (i do have an arty a7 35K, this might be too small, i guess?). According to the readme it shall be "easy" to add new accelerator hardware. Sadly my knowledge is still a bit limited around all the python-machinelearning-ecosystem, but if I understand it correctly you "just" need an openCL kernel and need to be able to shove the data back and forth somehow. Didn't have enough time to dive into it yet and still working on some other project, but this still tickles the back of my head and would be cool even if I could only run mnist on it. - [1] https://github.com/tinygrad/tinygrad/ https://github.com/tinygrad/tinygrad/

gh02t 2y ago
> but if I understand it correctly you "just" need an openCL kernel and need to be able to shove the data back and forth somehow. To use it with an FPGA accelerator you also have to build all the "hardware" to run said openCL kernel efficiently, manage data transfer, talk to the host, etc for the FPGA. This is very foreign if you're only used to doing software design and still very nontrivial even if you've done FPGA work, though I think there are some open hardware projects around doing this.
- dailykoder 2y ago
  Yeah, i think the, especially efficient, data transfer would be my biggest enemy. I did quite a lot FPGA stuff in recent years, mainly CPU design stuff, a little pipelining and some hardware-software-codesign. So I should just see it as a toy project, start with said mnist to get atleast something running, don't matter if it's efficient and then work my way up. For example I haven't done anything PCIe related yet, but I guess there is enough IP available
  - 15155 2y ago
    Transceivers are the only option for high-speed connectivity - this means PCIE or 100GbE.

gh02t 2y ago

> but if I understand it correctly you "just" need an openCL kernel and need to be able to shove the data back and forth somehow. To use it with an FPGA accelerator you also have to build all the "hardware" to run said openCL kernel efficiently, manage data transfer, talk to the host, etc for the FPGA. This is very foreign if you're only used to doing software design and still very nontrivial even if you've done FPGA work, though I think there are some open hardware projects around doing this.

dailykoder 2y ago
Yeah, i think the, especially efficient, data transfer would be my biggest enemy. I did quite a lot FPGA stuff in recent years, mainly CPU design stuff, a little pipelining and some hardware-software-codesign. So I should just see it as a toy project, start with said mnist to get atleast something running, don't matter if it's efficient and then work my way up. For example I haven't done anything PCIe related yet, but I guess there is enough IP available
- 15155 2y ago
  Transceivers are the only option for high-speed connectivity - this means PCIE or 100GbE.