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They state this as their reasoning so there must be merit in pursuing a smaller footprint: > Current industry trends are to adapt 32-bit RISC IP for microcontr

They state this as their reasoning so there must be merit in pursuing a smaller footprint: > Current industry trends are to adapt 32-bit RISC IP for microcontroller use, however their large 32x32 register files and loosely encoded instructions limit their absolute minimum footprint. So with the goal of a creating a performance and compact microprocessor IP, we need an 16-bit instruction set architecture (ISA). Not every application requires 32 bits and as you can see from some of the use cases, there might be a dozen of these in a design so minimal footprint is important.

RetroTechie 2y ago
Some 8-bit cpus allow combining some registers in pairs. Giving 16-bit values from otherwise 8-bit registers. Or have a few dedicated 16-bit registers. Couldn't the same be done in a 16-bit architecture? And cut the # of registers. Like 16x 16-bit registers, optionally used as 32-bit pairs (8 of those). None of this says anything about external memory sizes or such. Btw: RISC-V has an "-E" flavour which cuts the # of registers in half from 32 to 16, but is otherwise identical. There's even some (unofficial) RV16 candidates out there.
- tredre3 2y ago
  I think part of the goal for Turbo9 is to be used in the real world. By using an established ISA and maintaining binary compatibility, their CPU can be targeted by any tooling built for it over the past 40 years. Think of it: all existing documentation, code, compilers, assemblers, know-how, even existing compiled binaries! As soon as you create your own architecture, you're essentially a toy. Nobody will want to rely on your half finished C compiler for it, or your unmaintained patchset for LLVM, or be willing to learn verilog just to fill gaps in documentation. Even something as "simple" as changing registers on RISC-V will break most tooling and make most existing documentation impossible to rely on. Resulting in essentially a new architecture with a confusing name. Being a toy isn't a bad thing, it just wasn't their goal here.

RetroTechie 2y ago

Some 8-bit cpus allow combining some registers in pairs. Giving 16-bit values from otherwise 8-bit registers. Or have a few dedicated 16-bit registers. Couldn't the same be done in a 16-bit architecture? And cut the # of registers. Like 16x 16-bit registers, optionally used as 32-bit pairs (8 of those). None of this says anything about external memory sizes or such. Btw: RISC-V has an "-E" flavour which cuts the # of registers in half from 32 to 16, but is otherwise identical. There's even some (unofficial) RV16 candidates out there.

tredre3 2y ago
I think part of the goal for Turbo9 is to be used in the real world. By using an established ISA and maintaining binary compatibility, their CPU can be targeted by any tooling built for it over the past 40 years. Think of it: all existing documentation, code, compilers, assemblers, know-how, even existing compiled binaries! As soon as you create your own architecture, you're essentially a toy. Nobody will want to rely on your half finished C compiler for it, or your unmaintained patchset for LLVM, or be willing to learn verilog just to fill gaps in documentation. Even something as "simple" as changing registers on RISC-V will break most tooling and make most existing documentation impossible to rely on. Resulting in essentially a new architecture with a confusing name. Being a toy isn't a bad thing, it just wasn't their goal here.