3 ms·
Interesting that there is no cache (instead it's using a prefetch queue).. "Implement multi-cycle to reduce area / power", I guess it's not one-cycle per instr
by jhallenworld 2y ago
Interesting that there is no cache (instead it's using a prefetch queue).. "Implement multi-cycle to reduce area / power", I guess it's not one-cycle per instruction, so maybe not needed.
Well, where is the superscalar variant? :-) At least on an FPGA, there would be very diminishing returns for doing it. Even bypassing has bad effects on fMAX.
- PaulHoule 2y agoLately I've been curious about building things like display controllers and microprocessors on the FPGA. It was https://en.wikipedia.org/wiki/Transport_triggered_architecture https://en.wikipedia.org/wiki/Transport_triggered_architectu... that convinced me I could build a useful custom processor but it also got me to see how complex things get when you go pipelined, superscalar, depending on a cache, etc.