3 ms·

Yeah, but can compilers actually do the necessary magic when encountering something like: x = ((y & (1<<101)|(1<<102)) >> 10); My impression was always th

Yeah, but can compilers actually do the necessary magic when encountering something like: x = ((y & (1<<101)|(1<<102)) >> 10); My impression was always that the vector extensions are good for SIMD operations, but not "wide integer" operations, but I might be wrong of course (e.g. is bit-shifting across "lanes" even possible?)

acchow 2y ago
It's not really a compiler issue tho. SIMD is meant to pointwise map an operation across multiple "lanes" in a single operation. You can't have lane interdependence on the result.
- LegionMammal978 2y ago
  (V)PALIGNR shifts between lanes just fine, but only with byte granularity.
  - acchow 2y ago
    Because of the byte granularity, there's no interdependence between lanes. The result within a lane is not affected by the values of the other lanes.
eigenket 2y ago
On 64 bit computers you've been able to use 128 bit unsigned ints as a gcc extension for a long time now and the bit twiddling stuff works exactly as you'd expect. The relevant types are __int128 / unsigned __int128. Clang has something similar and my understanding is that c23's _BitInt will let you do this.
- flohofwoe 2y ago
  Yes, but compilers seem to disagree on whether they use a pair of 64-bit registers, or an SSE register under the hood (reusing link from a reply): https://godbolt.org/z/xEqrx5dY4 https://godbolt.org/z/xEqrx5dY4
jcranmer 2y ago
As it turns out, yes: https://godbolt.org/z/xEqrx5dY4 https://godbolt.org/z/xEqrx5dY4 SSE2 adds the PSRL/PSLL operators, which are basically i128 shift operators on vector registers (i.e., shift continues between lanes), so you can pretty easily map i128 to vector registers if you're only doing and/or/xor/shifts.
- pbsd 2y ago
  The 128-bit wide shifts PS{L,R}LDQ only have byte granularity. They're a special case of a byte shuffle.
  - acchow 2y ago
    The "Q" at the end is "quadword", so it's 64 bits (8 bytes).
    - pbsd 2y ago
      No, you're thinking of PS{R,L}LQ.
- acchow 2y ago
  No, it doesn't shift across 64-bit boundaries. Take a look at the gcc output in your link ``` movdqa xmm0, XMMWORD PTR [rdi] movdqa xmm1, xmm0 psrlq xmm0, 10 psrldq xmm1, 8 psllq xmm1, 54 por xmm0, xmm1 movdqa xmm1, XMMWORD PTR .LC0[rip] ``` That's a lot of psr and psl instructions for a "single 128-bit wide shift"...

acchow 2y ago

It's not really a compiler issue tho. SIMD is meant to pointwise map an operation across multiple "lanes" in a single operation. You can't have lane interdependence on the result.

LegionMammal978 2y ago
(V)PALIGNR shifts between lanes just fine, but only with byte granularity.
- acchow 2y ago
  Because of the byte granularity, there's no interdependence between lanes. The result within a lane is not affected by the values of the other lanes.

eigenket 2y ago

On 64 bit computers you've been able to use 128 bit unsigned ints as a gcc extension for a long time now and the bit twiddling stuff works exactly as you'd expect. The relevant types are __int128 / unsigned __int128. Clang has something similar and my understanding is that c23's _BitInt will let you do this.

flohofwoe 2y ago
Yes, but compilers seem to disagree on whether they use a pair of 64-bit registers, or an SSE register under the hood (reusing link from a reply): https://godbolt.org/z/xEqrx5dY4 https://godbolt.org/z/xEqrx5dY4

jcranmer 2y ago

As it turns out, yes: https://godbolt.org/z/xEqrx5dY4 https://godbolt.org/z/xEqrx5dY4 SSE2 adds the PSRL/PSLL operators, which are basically i128 shift operators on vector registers (i.e., shift continues between lanes), so you can pretty easily map i128 to vector registers if you're only doing and/or/xor/shifts.

pbsd 2y ago
The 128-bit wide shifts PS{L,R}LDQ only have byte granularity. They're a special case of a byte shuffle.
- acchow 2y ago
  The "Q" at the end is "quadword", so it's 64 bits (8 bytes).
  - pbsd 2y ago
    No, you're thinking of PS{R,L}LQ.
acchow 2y ago
No, it doesn't shift across 64-bit boundaries. Take a look at the gcc output in your link ``` movdqa xmm0, XMMWORD PTR [rdi] movdqa xmm1, xmm0 psrlq xmm0, 10 psrldq xmm1, 8 psllq xmm1, 54 por xmm0, xmm1 movdqa xmm1, XMMWORD PTR .LC0[rip] ``` That's a lot of psr and psl instructions for a "single 128-bit wide shift"...