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The end result seems to be that the two entries from that old post that have seen the most success, x86 and ARM, are essentially the RISCiest of the CISCs and t

The end result seems to be that the two entries from that old post that have seen the most success, x86 and ARM, are essentially the RISCiest of the CISCs and the CISCiest of the RISCs. A happy medium.

hmry 2y ago
Intel's new x86 extension (APX) is adding 16 more registers and three-register instructions. RISCification is still in progress.
- sapiogram 2y ago
  What's RISC about adding more registers?
  - ajross 2y ago
    The simple answer is that a big symmetric register set has always been a hallmark of RISC ISAs, because having lots of symmetric registers increases throughput by reducing compiler-generated spill/fill overhead and permits more permissive ABIs for leaf functions that need the extra space. The complicated answer is that, no, it's not especially "reduced" and you could implement all those other RISCy ideas in a much smaller set of GPRs without otherwise effecting the "RISCiness" of the design. But that answer is a little specious, since it's true of all the other RISCy traits too. Most of them stand alone, which is why the whole debate tends to be a little silly.
  - Symmetry 2y ago
    The name "RISC" is something we gave to a particular design philosophy, but not everything in that philosophy is summed up in the name. Classic RISC designs have 32 registers to make up for the lack of instructions that operate directly on memory addresses and to make things easier for the compiler and achieve good performance without load-op-store instructions.
fanf2 2y ago
The runner-up CISC, IBM z / 370, is also fairly RISCy.
- pclmulqdq 2y ago
  The runner-up RISC, IBM's POWER, is arguably more CISC-y than ARM.
  - brucehoult 2y ago
    I can't agree with that -- POWER has slightly simpler addressing modes, in that `lwu` etc are always and only pre-increment/decrement, and doesn't have load/store multiple (the most CISCy thing in arm32) at all. And also, obviously, not predication, either per-instruction or with anything like `IT*`.
    - pclmulqdq 2y ago
      ARM64 gets a lot closer to CISC than ARM32, honestly (aside from the "everything predicated" and "double word stores"), with a larger suite of weirder instructions. Predication is also a distinct feature of ARM instructions, not a generic CISC thing. POWER has instructions like RLIMI, DOZ, and STHBRX on the "complex" side. The RISC/CISC distinction is not just about addressing and accessing memory (register-register vs register-memory operations). The headline operations for x86 actually were more about the compute side rather than the memory side - things like the "AAD" instruction did a lot of computing work in one bite. There were also RISC register-memory machines at the time the distinction was meaningful.
      - brucehoult 2y ago
        > ARM64 gets a lot closer to CISC than ARM32 No way. Quite the opposite. ARM64 is quite similar to e.g. RISC-V in most respects other than the use of condition codes. > POWER has instructions like RLIMI, DOZ, and STHBRX on the "complex" side. There is nothing complex or "un-RISC" about any of those. RLIMI is similar to Arm32 BFI or Arm64 UBFM. DOZ is just subtract with the output zeroed if the MSB is 1. It is easily implemented with just a handful of straight-line instructions in any ISA with min/max or slt or for that matter asr i.e. in hardware with a simple combinatorial add-on to standard subtraction. STHBRX is just a little-endian store (on big-endian POWER). Plenty of other RISC ISAs (whether big-endian or little-endian) have that. > things like the "AAD" instruction did a lot of computing work in one bite Less than other ISAs with a one-shot decimal add instruction (or mode e.g. 6502). Once again, it's a very simple combinatorial circuit -- no CISCy microcode or control flow needed. > There were also RISC register-memory machines at the time the distinction was meaningful. Name one.
snvzz 2y ago
>the RISCiest of the CISCs and the CISCiest of the RISCs. A happy medium. Until RISC-V enters the conversation.
- thechao 2y ago
  If you actually dig into the details of RISC-V — especially the variable width extensions, it scratches all of my CISC-y itches just fine. Is it as CISC-y as ARM or x86? Not yet; not yet.

hmry 2y ago

Intel's new x86 extension (APX) is adding 16 more registers and three-register instructions. RISCification is still in progress.

sapiogram 2y ago
What's RISC about adding more registers?
- ajross 2y ago
  The simple answer is that a big symmetric register set has always been a hallmark of RISC ISAs, because having lots of symmetric registers increases throughput by reducing compiler-generated spill/fill overhead and permits more permissive ABIs for leaf functions that need the extra space. The complicated answer is that, no, it's not especially "reduced" and you could implement all those other RISCy ideas in a much smaller set of GPRs without otherwise effecting the "RISCiness" of the design. But that answer is a little specious, since it's true of all the other RISCy traits too. Most of them stand alone, which is why the whole debate tends to be a little silly.
- Symmetry 2y ago
  The name "RISC" is something we gave to a particular design philosophy, but not everything in that philosophy is summed up in the name. Classic RISC designs have 32 registers to make up for the lack of instructions that operate directly on memory addresses and to make things easier for the compiler and achieve good performance without load-op-store instructions.

fanf2 2y ago

The runner-up CISC, IBM z / 370, is also fairly RISCy.

pclmulqdq 2y ago
The runner-up RISC, IBM's POWER, is arguably more CISC-y than ARM.
- brucehoult 2y ago
  I can't agree with that -- POWER has slightly simpler addressing modes, in that `lwu` etc are always and only pre-increment/decrement, and doesn't have load/store multiple (the most CISCy thing in arm32) at all. And also, obviously, not predication, either per-instruction or with anything like `IT*`.
  - pclmulqdq 2y ago
    ARM64 gets a lot closer to CISC than ARM32, honestly (aside from the "everything predicated" and "double word stores"), with a larger suite of weirder instructions. Predication is also a distinct feature of ARM instructions, not a generic CISC thing. POWER has instructions like RLIMI, DOZ, and STHBRX on the "complex" side. The RISC/CISC distinction is not just about addressing and accessing memory (register-register vs register-memory operations). The headline operations for x86 actually were more about the compute side rather than the memory side - things like the "AAD" instruction did a lot of computing work in one bite. There were also RISC register-memory machines at the time the distinction was meaningful.
    - brucehoult 2y ago
      > ARM64 gets a lot closer to CISC than ARM32 No way. Quite the opposite. ARM64 is quite similar to e.g. RISC-V in most respects other than the use of condition codes. > POWER has instructions like RLIMI, DOZ, and STHBRX on the "complex" side. There is nothing complex or "un-RISC" about any of those. RLIMI is similar to Arm32 BFI or Arm64 UBFM. DOZ is just subtract with the output zeroed if the MSB is 1. It is easily implemented with just a handful of straight-line instructions in any ISA with min/max or slt or for that matter asr i.e. in hardware with a simple combinatorial add-on to standard subtraction. STHBRX is just a little-endian store (on big-endian POWER). Plenty of other RISC ISAs (whether big-endian or little-endian) have that. > things like the "AAD" instruction did a lot of computing work in one bite Less than other ISAs with a one-shot decimal add instruction (or mode e.g. 6502). Once again, it's a very simple combinatorial circuit -- no CISCy microcode or control flow needed. > There were also RISC register-memory machines at the time the distinction was meaningful. Name one.

snvzz 2y ago

>the RISCiest of the CISCs and the CISCiest of the RISCs. A happy medium. Until RISC-V enters the conversation.

thechao 2y ago
If you actually dig into the details of RISC-V — especially the variable width extensions, it scratches all of my CISC-y itches just fine. Is it as CISC-y as ARM or x86? Not yet; not yet.