5 ms·
Cost plays no role. Cost of bits at L2 and L3 are more or less the same. They are typically implemented using the same kind of transistors. The reason is late
by Tuna-Fish 2y ago
Cost plays no role.
Cost of bits at L2 and L3 are more or less the same. They are typically implemented using the same kind of transistors.
The reason is latency, plain and simple. Making a pool of memory larger always makes it slower to access, so to have a very fast pool you need it to be very small. The optimal solution is a hierarchical stack of pools of increasing size and latency. And if you had infinite free transistors, it would still be the same.
- credit_guy 2y agoI found this great link from Intel [1]. Apologies for my poor formatting of the table. | Memory _| Size __| Latency| Bandwidth | L1 cache | 32 KB _| 1 ns _| 1 TB/s | L2 cache | 256 KB | 4 ns _| 1 TB/s | L3 cache | 8 MB+ | 10x L2 | >400 GB/s | MCDRAM | ______| 2x L3 | 400 GB/s | DDR DIMMs| 4 GB-1 TB| 2x L3 | 100 GB/s [1] https://www.intel.com/content/www/us/en/developer/articles/technical/memory-performance-in-a-nutshell.html https://www.intel.com/content/www/us/en/developer/articles/t...
- hi-v-rocknroll 2y ago> Cost plays no role. 0. You're not going to have 32 GiB of SRAM anytime soon. 1. Amount of L3 translates into area which means cost. 1152 MiB of L3 on an 9684X ain't fucking free.
- Tuna-Fish 2y agoNone of that is what we are talking about. The question is, why is there a small L1, medium L2 and a large L3? Why not just have it all be L1? And cost plays no role in those decisions. Making the L1 or L2 larger would make them too slow. Only the size of L3 is limited by cost.