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So here's the scenario: you're using SystemVerilog, so Icarus does not work since it doesn't fully support it. You could use xsim (part of Xilinx Vivado)- it d

So here's the scenario: you're using SystemVerilog, so Icarus does not work since it doesn't fully support it. You could use xsim (part of Xilinx Vivado)- it does work, but yuck, it's part of Vivado. So you end up using ModelSim- only now it's QuestaSim, and Siemens has eliminated the low cost tier (also, I'm not a huge fan the ModelSim GUI). I'm mean you might as well use ncsim or vcs.. So Verilator is the answer! Except.. - It's a two-state simulator, so some reset bugs are not found. - Your Verilog-style testbench will not work. - No encrypted IP support. On the other hand: - Verilator is fast. This is a big deal for fuzzing tests. - The linting is awesome- it's good enough that you don't have to run the synthesis tool. - gtkwave works well with it (you must use the FST format "--trace-fst", not VCD), then you get enums and structures. Counterintuitively, structures show up as modules not signals, but you get used to it. You can also get free ModelSim as part of Lattice (or Questa as part of Altera) if you don't need the Xilinx IP.

pclmulqdq 2y ago
I have been bitten so many times by bugs in third-party IP that I almost never use it unless the company literally cannot build the thing that the IP provider is selling. Many companies instead buy the IP and then spend almost as much time as they would have needed to recreate it having back-and-forth conversations with their vendor sending bug reports and reproduction test cases. Verilator is amazing for building huge systems when you make that tradeoff. Yes, you will do a lot more RTL development for logic, but you have none of these vendor headaches and you get to write your testbenches in C++ and also run tests that are extremely long. A single computer can simulate an SoC design at reasonable speed.
pkkim 2y ago
The Antmicro team are doing good work with making Verilator support SystemVerilog / UVM tests but from what I understand it's not complete yet. I've also heard from various people that although Verilator is generally fast, it tends to choke on compiling sufficiently large designs, whereas the Cadence and Synopsys offerings eventually get it done. Still, Verilator is an awesome piece of software. Maybe the biggest thing recommending it: it's totally free, so the number of simulations you run in parallel is bounded by compute availability rather than licenses. Shameless plug: I'm a cofounder of silogy.io, which offers hosted Verilator and other Verilog sims, plus debugging and collab tools.

pclmulqdq 2y ago

I have been bitten so many times by bugs in third-party IP that I almost never use it unless the company literally cannot build the thing that the IP provider is selling. Many companies instead buy the IP and then spend almost as much time as they would have needed to recreate it having back-and-forth conversations with their vendor sending bug reports and reproduction test cases. Verilator is amazing for building huge systems when you make that tradeoff. Yes, you will do a lot more RTL development for logic, but you have none of these vendor headaches and you get to write your testbenches in C++ and also run tests that are extremely long. A single computer can simulate an SoC design at reasonable speed.

pkkim 2y ago

The Antmicro team are doing good work with making Verilator support SystemVerilog / UVM tests but from what I understand it's not complete yet. I've also heard from various people that although Verilator is generally fast, it tends to choke on compiling sufficiently large designs, whereas the Cadence and Synopsys offerings eventually get it done. Still, Verilator is an awesome piece of software. Maybe the biggest thing recommending it: it's totally free, so the number of simulations you run in parallel is bounded by compute availability rather than licenses. Shameless plug: I'm a cofounder of silogy.io, which offers hosted Verilator and other Verilog sims, plus debugging and collab tools.