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Memory Consistency Models: A Tutorial

• signa11 3y ago
  what is the "dense tome" that the author refers to in this link: http://www.morganclaypool.com/doi/abs/10.2200/S00346ED1V01Y201104CAC016 http://www.morganclaypool.com/doi/abs/10.2200/S00346ED1V01Y2... ? it seems to be coming up kinda 404 for me. thank you !
  • sdbbp 3y ago
    Probably "A Primer on Memory Consistency and Cache Coherence"
    • darkPotato 3y ago
      Hi, would you recommend this book in 2024?
      • CoastalCoder 3y ago
        FWIW, most of my recent knowledge on this topic comes from [0]. The programming-language-specific parts are more focused on C than C++ (which is my main focus), but I've still found it quite helpful. I haven't looked at the other sources people are mentioning though, so no idea how it compares. [0] https://cdn.kernel.org/pub/linux/kernel/people/paulmck/perfbook/perfbook.html https://cdn.kernel.org/pub/linux/kernel/people/paulmck/perfb...
        • darkPotato 3y ago
          Thank you, I will give your resource a read :)
          • CoastalCoder 3y ago
            You're welcome! But it's not a quick read. At least for me, it requires (a) a good reason for powering through it, (b) a good night's sleep, and (c) Adderall :) Just saying, it may not be the most effective / efficient way to learn what you want to know.
            • darkPotato 2y ago
              Ahaha, luckily /s I am a bit of a weirdo and I like to delve deeper into things related to my job. I was taught that a deeper understanding leads to better software/solutions and I strive to live up to my mentor dedication :)
              • collinvandyck76 2y ago
                > I was taught that a deeper understanding leads to better software/solutions aside from being fun, it just makes everything so much easier when it's not "magic"
      • anonymousDan 3y ago
        Yes
  • sdbbp 3y ago
    See also https://www.cs.cmu.edu/afs/cs/academic/class/15740-f18/www/papers/ieeemicro96-adve-consistency.pdf https://www.cs.cmu.edu/afs/cs/academic/class/15740-f18/www/p... and Gharachorloo's thesis paper.
    • signa11 3y ago
      @sdbbp, thank you kindly for the references, both are excellent !
• liblfds-temp 3y ago
  > A barrier instruction forces all memory operations before it to complete before any memory operation after it can begin. That is, a barrier instruction effectively reinstates sequential consistency at a particular point in program execution. > Of course, this is exactly the behavior we were trying to avoid by introducing store buffers and other optimizations. Barriers are an escape hatch to be used sparingly: they can cost hundreds of cycles. I may be wrong, but I think to readers who do not already know what barriers do and are, this makes barriers seem like blocking behaviours.
  • throwaway17_17 3y ago
    Just to clarify your comment via a question: are you pointing out that barrier instructions are a scheduling ‘issue’ that the processor uses to order instructions versus something like a memory read that actually requires a pause in the execution of instructions?
    • liblfds-temp 2y ago
      Mmm. Sort of the former, but really my thought was this : "you have a barrier, fine, but that does not mean once you hit/pass the barrier, all prior read/writes are complete - in fact, the completion of earlier reads/writes only occurs at the first read/write after the barrier".
  • Maxatar 3y ago
    Barriers can induce blocking behavior though. A store barrier followed by a store operation can result in a blocking operation until the store buffer is flushed, and similarly for a load barrier.
  • gpderetta 3y ago
    The usual way that barriers were implemented was to simply stall the CPU pipeline. So yes, they do indeed have blocking semantics. IIRC mfence still does stall the pipeline on x86, but I think the CPU is a bit smarter for locked instructions.
• CoastalCoder 3y ago
  I'm about to move into ARM development for a new-ish AI accelerator. Until now, I've mostly developed for x86. In preparation for this, I've been reading up on ARM's looser memory consistency model, and C++'s rules regarding this. It's been pretty eye-opening. I'm looking forward to seeing how much that ARM codebase takes advantage of the weaker guarantees that ARM permits. It seems like a trade-off of scalability vs. correct-code complexity.
• anonymousDan 3y ago
  It's mentioned briefly at the end of the article but this book from Morgan & Claypool is great: http://www.morganclaypool.com/doi/abs/10.2200/S00346ED1V01Y201104CAC016 http://www.morganclaypool.com/doi/abs/10.2200/S00346ED1V01Y2...