3 ms·
I'm saying that an atomic RMW is going to get the cache line in "exclusive" state, (in typical MESI protocol) but that if you are trying to gin up the equivalen
by dbcurtis 2y ago
I'm saying that an atomic RMW is going to get the cache line in "exclusive" state, (in typical MESI protocol) but that if you are trying to gin up the equivalent with spin locks you need to think through how that plays out, as the reads might be in "shared" state.
- moonchild 2y agoI still don't see what you're getting at. What is the implication of this for software? The implementation of the cache coherency protocol is largely opaque to software.