4 ms·
I see no mention of tamper-resistance/self-destruct features? Power glitch detection, mechanisms to detect decapping/stripping, wire mesh shielding, protection
by dhx 14y ago
I see no mention of tamper-resistance/self-destruct features?
Power glitch detection, mechanisms to detect decapping/stripping, wire mesh shielding, protection against ultra-violet laser stimulation of transistors, ... are all important.
For those interested in further reading, Security Engineering[1] by Ross Anderson contains a section on chip security. Another paper[2] by Ross Anderson and Markus Kuhn (1996) provides additional background.
[1] https://www.cl.cam.ac.uk/~rja14/book.html https://www.cl.cam.ac.uk/~rja14/book.html
[2] https://www.cl.cam.ac.uk/~rja14/tamper.html https://www.cl.cam.ac.uk/~rja14/tamper.html
- JL2010 14y ago"Unlike SRAM-based FPGAs or conventional ASIC solutions, ProASIC3/E devices offer one of the highest levels of design security in the industry. In fact, ProASIC3/E devices bring new levels of security to the FPGA market place. An FPGA industry first, secure ISP is performed using the industry-standard 128- bit AES block cipher algorithm. Reprogramming can be securely performed in-system to support future design iterations and field upgrades with peace of mind that valuable IP cannot be compromised or copied." ISP stands for in-system-programming
- __alexs 14y agoThey do a special "military" version for which they don't publicly publish the featureset.