I am also aware the Xilinx sets their own clock specs annoyingly conservatively, and I think they do it to preserve device lifetime or something similar. Howev

I am also aware the Xilinx sets their own clock specs annoyingly conservatively, and I think they do it to preserve device lifetime or something similar. However, I did want to clarify whether you were overvolting these things or just raising the clock frequency. I have run into issues where you do get a dud FPGA that is just a lot slower than other FPGAs of its speed bin (it must have come from the edge of the wafer or something), and debugging that is pretty annoying.