3 ms·

The chip in question seems to be an Actel Microsemi ProASIC3 (PA3) [1,2], given the hints in the screenshot of the paper. [1] http://www.actel.com/products/pa3

by raphman 14y ago

The chip in question seems to be an Actel Microsemi ProASIC3 (PA3) [1,2], given the hints in the screenshot of the paper. [1] http://www.actel.com/products/pa3/ http://www.actel.com/products/pa3/ [2] http://www.actel.com/documents/pa3_faq.html http://www.actel.com/documents/pa3_faq.html (I guess there is no real advantage in keeping this obscured)

femto 14y ago
Ouch, as it would be quite easy to think that you are "safe" if you spin your own processor from scratch and run it on an FPGA. Who's to say that manufacturing in China means the backdoor was injected by China? I would have thought the US is just as likely a source, given that the design came from there. Surely the US government would love having access to FPGAs in foreign systems? The cynic in me says that Cambridge needs to keep poking, as they might find two backdoors: one inserted by the US, the other by China.
dhx 14y ago
I see no mention of tamper-resistance/self-destruct features? Power glitch detection, mechanisms to detect decapping/stripping, wire mesh shielding, protection against ultra-violet laser stimulation of transistors, ... are all important. For those interested in further reading, Security Engineering[1] by Ross Anderson contains a section on chip security. Another paper[2] by Ross Anderson and Markus Kuhn (1996) provides additional background. [1] https://www.cl.cam.ac.uk/~rja14/book.html https://www.cl.cam.ac.uk/~rja14/book.html [2] https://www.cl.cam.ac.uk/~rja14/tamper.html https://www.cl.cam.ac.uk/~rja14/tamper.html
- JL2010 14y ago
  "Unlike SRAM-based FPGAs or conventional ASIC solutions, ProASIC3/E devices offer one of the highest levels of design security in the industry. In fact, ProASIC3/E devices bring new levels of security to the FPGA market place. An FPGA industry first, secure ISP is performed using the industry-standard 128- bit AES block cipher algorithm. Reprogramming can be securely performed in-system to support future design iterations and field upgrades with peace of mind that valuable IP cannot be compromised or copied." ISP stands for in-system-programming
- __alexs 14y ago
  They do a special "military" version for which they don't publicly publish the featureset.
Nrsolis 14y ago
Is there ANY chance that this is a bit of a tempest in a teapot? I can envision a scenario where this "backdoor" is actually part of the designed-in security features of the chip designed to prevent an unauthorized party from reading out the FPGA "programming" as it were. As such, it's conceivable that there might be multiple keys or even a series of "transport" or "default" keys that are similar to those found on ISO smartcards. What we might be looking at is a "feature" as opposed to a "backdoor." In any case, this sort of thing only becomes a critical security breach if the application you're using the chip in depends on periodic (or boot-time) reprogramming of the FPGA. In either case, either the physical security or the trust chain of your firmware loads is broken. As we all know, key management and side channel attacks are the hardest part of implementing a secure crypto system, so is this really news?

by raphman 14y ago

femto 14y ago

Ouch, as it would be quite easy to think that you are "safe" if you spin your own processor from scratch and run it on an FPGA. Who's to say that manufacturing in China means the backdoor was injected by China? I would have thought the US is just as likely a source, given that the design came from there. Surely the US government would love having access to FPGAs in foreign systems? The cynic in me says that Cambridge needs to keep poking, as they might find two backdoors: one inserted by the US, the other by China.

dhx 14y ago

I see no mention of tamper-resistance/self-destruct features? Power glitch detection, mechanisms to detect decapping/stripping, wire mesh shielding, protection against ultra-violet laser stimulation of transistors, ... are all important. For those interested in further reading, Security Engineering[1] by Ross Anderson contains a section on chip security. Another paper[2] by Ross Anderson and Markus Kuhn (1996) provides additional background. [1] https://www.cl.cam.ac.uk/~rja14/book.html https://www.cl.cam.ac.uk/~rja14/book.html [2] https://www.cl.cam.ac.uk/~rja14/tamper.html https://www.cl.cam.ac.uk/~rja14/tamper.html

JL2010 14y ago
"Unlike SRAM-based FPGAs or conventional ASIC solutions, ProASIC3/E devices offer one of the highest levels of design security in the industry. In fact, ProASIC3/E devices bring new levels of security to the FPGA market place. An FPGA industry first, secure ISP is performed using the industry-standard 128- bit AES block cipher algorithm. Reprogramming can be securely performed in-system to support future design iterations and field upgrades with peace of mind that valuable IP cannot be compromised or copied." ISP stands for in-system-programming
__alexs 14y ago
They do a special "military" version for which they don't publicly publish the featureset.

Nrsolis 14y ago

Is there ANY chance that this is a bit of a tempest in a teapot? I can envision a scenario where this "backdoor" is actually part of the designed-in security features of the chip designed to prevent an unauthorized party from reading out the FPGA "programming" as it were. As such, it's conceivable that there might be multiple keys or even a series of "transport" or "default" keys that are similar to those found on ISO smartcards. What we might be looking at is a "feature" as opposed to a "backdoor." In any case, this sort of thing only becomes a critical security breach if the application you're using the chip in depends on periodic (or boot-time) reprogramming of the FPGA. In either case, either the physical security or the trust chain of your firmware loads is broken. As we all know, key management and side channel attacks are the hardest part of implementing a secure crypto system, so is this really news?