Look at the (non-Zynq) VCU128 board for an example. The HBM2 is on the PL side, and the interconnect is via a die-to-die interface. So the 32 AXI3 interfaces

Look at the (non-Zynq) VCU128 board for an example. The HBM2 is on the PL side, and the interconnect is via a die-to-die interface. So the 32 AXI3 interfaces to HBM2 here are hard silicon, not FPGA I/O pins.