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I wonder if it's practical to do ECC on 64 bit words instead of bytes. A 13% price increase (or capacity drop for the same DRAM price) is substantial and might

I wonder if it's practical to do ECC on 64 bit words instead of bytes. A 13% price increase (or capacity drop for the same DRAM price) is substantial and might justify the penny pinching, 1.5% is negligible if it leads to a similar stability increase as standard ECC DRAM. If you are often getting more then one bit flip per 64 bit word, than that RAM is garbage anyway.

baq 2y ago
this a loaded question. anyone interested in the topic should absolutely start from reading up on https://en.wikipedia.org/wiki/Error_correction_code https://en.wikipedia.org/wiki/Error_correction_code and only then start looking into the engineering side, starting with https://en.wikipedia.org/wiki/ECC_memory https://en.wikipedia.org/wiki/ECC_memory, notably some benchmarks reported 25% performance hits (not sure if it's real or sales propaganda.)
- cornholio 2y ago
  I clearly am not talking about in-band ECC (storing the error detection data inside the program accessible RAM) that the 25% performance drop refers to.
pclmulqdq 2y ago
ECC is done on 8-byte words. The basic form of RAM ECC is called "SECDED" ECC, and is an 8-bit hamming code that can correct one error silently and detect any two. It's not just a parity bit. The number of ECC bits needed for any error correction level on n bits are proportional to log(n). DDR actually operates in bursts of 4 or 8 64-bit words (+8 ECC), so you can make a better ECC using all 32 or 64 bits to cover the full burst rather than covering each 8 bytes separately.
- ajross 2y ago
  In point of fact most L2+ caches are already ECC'd on whole cache lines, as I understand it. At the level of on-SOC integration this makes a little more sense [1] as it effectively "improves yield" by recovering marginal cache regions that wouldn't otherwise pass tests. [1] vs. the semi-religious flame war about DRAM ECC in which I won't engage. People get nuts over this, and IMHO the actual data is awfully inconclusive.
  - pclmulqdq 2y ago
    Yes, most modern CPUs seem to do RAM ECC at the level of cache lines, too. That lets them do things like erasure coding to cover you if an entire RAM chip goes bad. SECDED ECC is the academic example.

baq 2y ago

this a loaded question. anyone interested in the topic should absolutely start from reading up on https://en.wikipedia.org/wiki/Error_correction_code https://en.wikipedia.org/wiki/Error_correction_code and only then start looking into the engineering side, starting with https://en.wikipedia.org/wiki/ECC_memory https://en.wikipedia.org/wiki/ECC_memory, notably some benchmarks reported 25% performance hits (not sure if it's real or sales propaganda.)

cornholio 2y ago
I clearly am not talking about in-band ECC (storing the error detection data inside the program accessible RAM) that the 25% performance drop refers to.

pclmulqdq 2y ago

ECC is done on 8-byte words. The basic form of RAM ECC is called "SECDED" ECC, and is an 8-bit hamming code that can correct one error silently and detect any two. It's not just a parity bit. The number of ECC bits needed for any error correction level on n bits are proportional to log(n). DDR actually operates in bursts of 4 or 8 64-bit words (+8 ECC), so you can make a better ECC using all 32 or 64 bits to cover the full burst rather than covering each 8 bytes separately.

ajross 2y ago
In point of fact most L2+ caches are already ECC'd on whole cache lines, as I understand it. At the level of on-SOC integration this makes a little more sense [1] as it effectively "improves yield" by recovering marginal cache regions that wouldn't otherwise pass tests. [1] vs. the semi-religious flame war about DRAM ECC in which I won't engage. People get nuts over this, and IMHO the actual data is awfully inconclusive.
- pclmulqdq 2y ago
  Yes, most modern CPUs seem to do RAM ECC at the level of cache lines, too. That lets them do things like erasure coding to cover you if an entire RAM chip goes bad. SECDED ECC is the academic example.