4 ms·
That is a trade-off towards density that seems not worth it where all it would take is a 16 bit NOP to pad and a few more bytes of memory to save on transistors
by Pet_Ant 3y ago
That is a trade-off towards density that seems not worth it where all it would take is a 16 bit NOP to pad and a few more bytes of memory to save on transistors of implementation.
Maybe they did the actual math and figured it's still cheaper? Might be worth it.
- __s 2y agoSiFive slides: https://s3-us-west-1.amazonaws.com/groupsioattachments/103890/101922590/353/0?AWSAccessKeyId=AKIAJECNKOVMCCU3ATNQ&Expires=1714505439&Signature=fpKsoNeGeZ80dHXMc2IPvEf8QOA%3D&response-content-disposition=inline%3B+filename%3D%22RISCV-20231004-C.pdf%22 https://s3-us-west-1.amazonaws.com/groupsioattachments/10389... Their argument is that since eventually there'll be 8 byte instructions, those will have the same cache line issues (tho that could be addressed by requiring 8 byte instructions be 8 byte aligned)