The article describes package failures mostly near TSVs and solder bumps presumably at the connections between chips not the oxide layers. In my experience thes

The article describes package failures mostly near TSVs and solder bumps presumably at the connections between chips not the oxide layers. In my experience these BEOL are a few micron metal min feature size for the routing/vias and larger for bumps. I haven't seen the latest stuff so maybe things have change significantly with the new MCMs in the last 3 years, but I'm doubtful. If I had to guess, these failures are at the power connections and so the solution is just more connections since the migration is very nonlinear with temp & current.