3 ms·
Well, yes. Planned obsolescence and all that. But what the article describes, and what my experience as a VLSI designer is that as feature sizes decreases, bei
by JoachimS 2y ago
Well, yes. Planned obsolescence and all that.
But what the article describes, and what my experience as a VLSI designer is that as feature sizes decreases, being able to just be able to guarantee a specified lifetime given environmental limits (ambient and die temperature, voltage and current supply including stability etc) is a very hard problem. And is getting harder. Just the statistical variance in the wafer production process steps (amount of molecules deposited) will make migration harder to estimate and handle.
A few SiO2 molecules more or less in thickness of an oxide layer that is 10000 molecules thick is not very important. But when the layer is supposed to be 10 molecules thick, 12 or 8 molecules corresponds to a huge difference in leakage.
So stating a minimum lifetime is what you do. A lifetime where at least 99% (or so) of the device still works reliably. Not to increase sales, but to avoid getting class action suits, having to pay out too much in refund, replace devices etc.
- kurthr 2y agoThe article describes package failures mostly near TSVs and solder bumps presumably at the connections between chips not the oxide layers. In my experience these BEOL are a few micron metal min feature size for the routing/vias and larger for bumps. I haven't seen the latest stuff so maybe things have change significantly with the new MCMs in the last 3 years, but I'm doubtful. If I had to guess, these failures are at the power connections and so the solution is just more connections since the migration is very nonlinear with temp & current.