3 ms·

Does anyone know what clock speeds we might be able to expect from this?

drmpeg 3y ago
This page says 50 MHz. https://github.com/rejunity/z80-open-silicon/blob/main/docs/info.md https://github.com/rejunity/z80-open-silicon/blob/main/docs/...
- tyingq 3y ago
  Interesting. Saw this on the Wishbone Z80 project notes: "Guy Hutchison (see TV80 project) has synthesized an early version of the core in a 130nm TSMC process. He determined the design to contain about 20k gates and run at about 240 Mhz. While the speed is somewhat less than "target", optimizations of the logic should increase this somewhat." Guy Hutchison's TV80 is also mentioned on this project's page.
- swetland 3y ago
  That's the expected clock rate for the TT07 run... but Tiny Tapeout designs only have 8 in, 8 out, and 8 bidirectional IOs (plus a reset and clock input) available, so they're using a multiplexing strategy where the Z80 clock runs at 1/4 of the base clock rate and alternates between control signals, A0-A7, control signals, and A8-A15 on the OUT pins: https://github.com/rejunity/z80-open-silicon/blob/68438f00192e7b2388163e198b330567e6133cb7/src/tt_um_rejunity_z80.v#L24 https://github.com/rejunity/z80-open-silicon/blob/68438f0019... So you'd get an effective 12.5MHz Z80 clock and need a bit of external logic to demultiplex the full IO interface. Still not too shabby! The goal (per the project README) appears to be to prototype with TT07 and then look into taping out standalone with ChipIgnite in QFN44 and DIP40 packages (which would be able to have the full traditional Z80 bus interface and run at the full clock rate).
Dwedit 3y ago
If you were designing a new compatible processor for older systems, the limiting factor would be the memory bus. A cache would be necessary to get high speeds. The cache would need to know about all bank-switching performed by the system, and understand how the memory banks are mapped into the memory space. Could have: * Plain read-only memory (you cache this) * Plain RAM not shared with other devices (you cache this) * Memory-mapped IO (you don't cache this) * RAM shared with other devices where the other device does not write there, such as video memory (write-through cache, full read cache) * RAM shared with other devices where the other device can write there (don't cache this)
- Retr0id 3y ago
  IIRC this is what the people making swap-in accelerators for 6502 chess computers are doing
  - Someone 3y ago
    Because it’s easy to ‘cache’ the entire memory of the host system, it’s better described as a new computer that only slows down to access the memory locations that affect I/O (video, audio, keyboard, I/O ports, etc.) https://www.e-basteln.de/computing/65f02/65f02/ https://www.e-basteln.de/computing/65f02/65f02/: “The idea is to use this as a “universal” accelerator for 6502 and 65C02-based host computers – just plug it into the CPU socket. The only thing the FPGA board needs to know about its host is the memory map: Where does the host have memory-mapped I/O? Up to 16 different memory maps can be stored in the FPGA, and selected via a mini DIP switch. Upon power-on, the 65F02 grabs the complete RAM and ROM content from the host and copies it into the on-chip RAM, except for the I/O area. Then the CPU gets going, using the internal memory at 100 MHz for all bus accesses except for any I/O addresses – for these, the internal CPU pauses, and an external bus cycle is started at whatever the external clock speed is.”
    - Dwedit 3y ago
      Speaking of new computers slowing down to access IO, someone managed to add an ISA slot to new PCs by using pin headers normally used by TPM devices. It's called the "dISAppointment".

This page says 50 MHz. https://github.com/rejunity/z80-open-silicon/blob/main/docs/info.md https://github.com/rejunity/z80-open-silicon/blob/main/docs/...

tyingq 3y ago
Interesting. Saw this on the Wishbone Z80 project notes: "Guy Hutchison (see TV80 project) has synthesized an early version of the core in a 130nm TSMC process. He determined the design to contain about 20k gates and run at about 240 Mhz. While the speed is somewhat less than "target", optimizations of the logic should increase this somewhat." Guy Hutchison's TV80 is also mentioned on this project's page.
swetland 3y ago
That's the expected clock rate for the TT07 run... but Tiny Tapeout designs only have 8 in, 8 out, and 8 bidirectional IOs (plus a reset and clock input) available, so they're using a multiplexing strategy where the Z80 clock runs at 1/4 of the base clock rate and alternates between control signals, A0-A7, control signals, and A8-A15 on the OUT pins: https://github.com/rejunity/z80-open-silicon/blob/68438f00192e7b2388163e198b330567e6133cb7/src/tt_um_rejunity_z80.v#L24 https://github.com/rejunity/z80-open-silicon/blob/68438f0019... So you'd get an effective 12.5MHz Z80 clock and need a bit of external logic to demultiplex the full IO interface. Still not too shabby! The goal (per the project README) appears to be to prototype with TT07 and then look into taping out standalone with ChipIgnite in QFN44 and DIP40 packages (which would be able to have the full traditional Z80 bus interface and run at the full clock rate).

Dwedit 3y ago

If you were designing a new compatible processor for older systems, the limiting factor would be the memory bus. A cache would be necessary to get high speeds. The cache would need to know about all bank-switching performed by the system, and understand how the memory banks are mapped into the memory space. Could have: * Plain read-only memory (you cache this) * Plain RAM not shared with other devices (you cache this) * Memory-mapped IO (you don't cache this) * RAM shared with other devices where the other device does not write there, such as video memory (write-through cache, full read cache) * RAM shared with other devices where the other device can write there (don't cache this)

Retr0id 3y ago
IIRC this is what the people making swap-in accelerators for 6502 chess computers are doing
- Someone 3y ago
  Because it’s easy to ‘cache’ the entire memory of the host system, it’s better described as a new computer that only slows down to access the memory locations that affect I/O (video, audio, keyboard, I/O ports, etc.) https://www.e-basteln.de/computing/65f02/65f02/ https://www.e-basteln.de/computing/65f02/65f02/: “The idea is to use this as a “universal” accelerator for 6502 and 65C02-based host computers – just plug it into the CPU socket. The only thing the FPGA board needs to know about its host is the memory map: Where does the host have memory-mapped I/O? Up to 16 different memory maps can be stored in the FPGA, and selected via a mini DIP switch. Upon power-on, the 65F02 grabs the complete RAM and ROM content from the host and copies it into the on-chip RAM, except for the I/O area. Then the CPU gets going, using the internal memory at 100 MHz for all bus accesses except for any I/O addresses – for these, the internal CPU pauses, and an external bus cycle is started at whatever the external clock speed is.”
  - Dwedit 3y ago
    Speaking of new computers slowing down to access IO, someone managed to add an ISA slot to new PCs by using pin headers normally used by TPM devices. It's called the "dISAppointment".