4 ms·

What Tiny Tapeout is doing is amazing. Who would have thought that makers and students could have their own chip design made real for so little money? The tool

by Renaud 2y ago

What Tiny Tapeout is doing is amazing. Who would have thought that makers and students could have their own chip design made real for so little money? The tools look amazing as well. You'll won't design the next Intel CPU on that 130nm process but to think that the Z80 will fit on 0.064 mm2 is just amazing. It's great that there will still be an alternative to the official chip now that it won't be manufactured any more. Now I want that gorgeous mauve ceramic package with a gold-plated cover over the chip... https://twitter.com/l_vanek/status/1783557817133039738/photo/1 https://twitter.com/l_vanek/status/1783557817133039738/photo... https://tinytapeout.com/ https://tinytapeout.com/

chx 2y ago
To save a click > 160 x 100 um tile + ASIC + demonstration board: The standard price is $300 plus shipping. > However, Efabless is sponsoring a special early bird offer of $150 (plus shipping), limited to one order per person. > Each extra tile is $50, and extra analog pins start from $40 per pin. Unless I am badly mistaken 160 x 100 um is .16 x .1 mm which means the tile is 0.016 mm2 meaning a 0.064 mm2 die takes four slots?
- mk_stjames 2y ago
  Yes it is taking up a 2x2 tile on the tinytapeout. https://app.tinytapeout.com/projects/668 https://app.tinytapeout.com/projects/668
- rowanG077 2y ago
  I could not find the pin capabilities. Is it possible to build an sdram controller or even drive ddr?
ashleyn 2y ago
130nm process puts them at roughly Pentium III era. Not bad!
- rvense 2y ago
  That's wild. A Pentium III would still be useful in a pinch. How big was a P3 die, though?
  - Someone 2y ago
    https://en.wikipedia.org/wiki/Pentium_III#Katmai https://en.wikipedia.org/wiki/Pentium_III#Katmai: “The Katmai contains 9.5 million transistors, not including the 512 Kbytes L2 cache (which adds 25 million transistors), and has dimensions of 12.3 mm by 10.4 mm (128 mm²). It is fabricated in Intel's P856.5 process, a 250 nm complementary metal–oxide–semiconductor (CMOS) process with five levels of aluminum interconnect” That’s 2,000 times the area of this 0.064 mm² Z80. https://en.wikipedia.org/wiki/Pentium_III#Tualatin https://en.wikipedia.org/wiki/Pentium_III#Tualatin: “The third revision, Tualatin (80530), was a trial for Intel's new 130 nm process” I can’t easily find the die size if that.
    - unnah 2y ago
      On that kind of process, you could make a 1024-core Z80 machine, leaving half the area for memory, interconnect and I/O. With suitably smart programming and an embarrassingly parallel problem, it might even be able to beat a Pentium III in performance... although it looks like the single-core Pentium III can run 128-bit SSE instructions at 2 cycles per instruction.
      - Someone 2y ago
        Suitably smart programming and a problem that suits the hardware. I doubt there are many of the latter. A Z80 has a 4-bit ALU (https://en.wikipedia.org/wiki/Zilog_Z80#Microarchitecture https://en.wikipedia.org/wiki/Zilog_Z80#Microarchitecture), making even integer addition take quite a few cycles (15 for 16-bit addition, reading http://www.z80.info/z80time.txt http://www.z80.info/z80time.txt) And then there’s the clock speed difference. The first Pentium III ran at 450MHz, the fastest Z80 at 50MHz (https://en.wikipedia.org/wiki/Zilog_eZ80 https://en.wikipedia.org/wiki/Zilog_eZ80) I think those two combined already will cost you a factor of around 100 in speed versus that pipelined Z80, much more versus a Z80 proper. Things get worse if you want to add or subtract 32- or 64-bit integers (another factor of 2 or 4, ballpark) If you want to do integer multiplication and division of any size and all floating point operations you will have to do those in software, and likely lose whatever speed advantage you might still have. O, and each core will be limited to 64kB of memory. Those interconnects better be fast and use DMA, so you can keep computing while you shuffle data around.

by Renaud 2y ago

chx 2y ago

To save a click > 160 x 100 um tile + ASIC + demonstration board: The standard price is $300 plus shipping. > However, Efabless is sponsoring a special early bird offer of $150 (plus shipping), limited to one order per person. > Each extra tile is $50, and extra analog pins start from $40 per pin. Unless I am badly mistaken 160 x 100 um is .16 x .1 mm which means the tile is 0.016 mm2 meaning a 0.064 mm2 die takes four slots?

mk_stjames 2y ago
Yes it is taking up a 2x2 tile on the tinytapeout. https://app.tinytapeout.com/projects/668 https://app.tinytapeout.com/projects/668
rowanG077 2y ago
I could not find the pin capabilities. Is it possible to build an sdram controller or even drive ddr?

ashleyn 2y ago

130nm process puts them at roughly Pentium III era. Not bad!

rvense 2y ago
That's wild. A Pentium III would still be useful in a pinch. How big was a P3 die, though?
- Someone 2y ago
  https://en.wikipedia.org/wiki/Pentium_III#Katmai https://en.wikipedia.org/wiki/Pentium_III#Katmai: “The Katmai contains 9.5 million transistors, not including the 512 Kbytes L2 cache (which adds 25 million transistors), and has dimensions of 12.3 mm by 10.4 mm (128 mm²). It is fabricated in Intel's P856.5 process, a 250 nm complementary metal–oxide–semiconductor (CMOS) process with five levels of aluminum interconnect” That’s 2,000 times the area of this 0.064 mm² Z80. https://en.wikipedia.org/wiki/Pentium_III#Tualatin https://en.wikipedia.org/wiki/Pentium_III#Tualatin: “The third revision, Tualatin (80530), was a trial for Intel's new 130 nm process” I can’t easily find the die size if that.
  - unnah 2y ago
    On that kind of process, you could make a 1024-core Z80 machine, leaving half the area for memory, interconnect and I/O. With suitably smart programming and an embarrassingly parallel problem, it might even be able to beat a Pentium III in performance... although it looks like the single-core Pentium III can run 128-bit SSE instructions at 2 cycles per instruction.
    - Someone 2y ago
      Suitably smart programming and a problem that suits the hardware. I doubt there are many of the latter. A Z80 has a 4-bit ALU (https://en.wikipedia.org/wiki/Zilog_Z80#Microarchitecture https://en.wikipedia.org/wiki/Zilog_Z80#Microarchitecture), making even integer addition take quite a few cycles (15 for 16-bit addition, reading http://www.z80.info/z80time.txt http://www.z80.info/z80time.txt) And then there’s the clock speed difference. The first Pentium III ran at 450MHz, the fastest Z80 at 50MHz (https://en.wikipedia.org/wiki/Zilog_eZ80 https://en.wikipedia.org/wiki/Zilog_eZ80) I think those two combined already will cost you a factor of around 100 in speed versus that pipelined Z80, much more versus a Z80 proper. Things get worse if you want to add or subtract 32- or 64-bit integers (another factor of 2 or 4, ballpark) If you want to do integer multiplication and division of any size and all floating point operations you will have to do those in software, and likely lose whatever speed advantage you might still have. O, and each core will be limited to 64kB of memory. Those interconnects better be fast and use DMA, so you can keep computing while you shuffle data around.