An interesting statistic from the Shakti[1] project - after building a 5-stage RISC-V core with an FPU, the same team had a reason to write an x86 decoder. The

An interesting statistic from the Shakti[1] project - after building a 5-stage RISC-V core with an FPU, the same team had a reason to write an x86 decoder. The _decode_ stage of the x86 alone was bigger than the entire pipeline of the RISC-V core. [1] https://shakti.org.in https://shakti.org.in