4 ms·
> This 1.6nm process will put them around 230 MTr/mm2 Would it be that x2 (for front & back)? E.g., 230 on front side and another 230 on back side = 460 MTr/m
by alberth 3y ago
> This 1.6nm process will put them around 230 MTr/mm2
Would it be that x2 (for front & back)?
E.g., 230 on front side and another 230 on back side = 460 MTr/mm2 TOTAL
- zeusk 3y agoBSPDN is not about putting devices on the front and back, the logic layer is still mostly 2D, it's about the power connects moving to the back of the chip so there's less interference with logic and larger wiring can be used.