2 ms·
Re 4, cpus already have huge caches. L1s sizes are limited by latency constraints, not area. CPUs are power limited, not area limited (see dark silicon) and des
by gpderetta 3y ago
Re 4, cpus already have huge caches. L1s sizes are limited by latency constraints, not area. CPUs are power limited, not area limited (see dark silicon) and designers find creative ways to use otherwise unused space (hence the giant SIMD ALUs).
- sudosysgen 3y agoThe L1 latency constraint is a size constraint - if you increase the L1 size, you simply cannot avoid increasing L1 latency.
- gpderetta 3y agoThat's what I meant: for performance considerations, L1 latency must be limited to single digit cycles on a general purpose CPU, hence L1 size is capped.