I'm also clueless. First search brings up https://www.tomshardware.com/news/intel-details-powervia-backside-power-delivery-network https://www.tomshardware.com/

I'm also clueless. First search brings up https://www.tomshardware.com/news/intel-details-powervia-backside-power-delivery-network https://www.tomshardware.com/news/intel-details-powervia-bac... with a nice diagram It looks like the topology for backside moves the transistors to the middle so "singal wires and power wires are decoupled and optimized separately" instead of "compete[ing] for the same resources at every metal layer"